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LAN9252/ML 数据表(PDF) 107 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 107 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 107
LAN9252
Figure 10-4 illustrates a typical single and multiple register read.
10.2.4.2
Fast Read
The Read at higher speed instruction inputs the instruction code and the address and dummy bytes one bit per clock
and outputs the data one bit per clock. In SQI mode, the instruction code and the address and dummy bytes are input
four bits per clock and the data is output four bits per clock. This instruction is supported in SPI and SQI bus protocols
with clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit FASTREAD instruction,
0Bh, is input into the SI/SIO[0] pin, followed by the two address bytes and 1 dummy byte. For SQI mode, the 8-bit FAS-
TREAD instruction is input into the SIO[3:0] pins, followed by the two address bytes and 3 dummy bytes. The address
bytes specify a BYTE address within the device.
On the falling clock edge following the rising edge of the last dummy bit (or nibble), the SO/SIO[1] pin is driven starting
with the msb of the LSB of the selected register. For SQI mode, SIO[3:0] are driven starting with the msn of the LSB of
the selected register. The remaining register bits are shifted out on subsequent falling clock edges.
The SCS# input is brought inactive to conclude the cycle. The SO/SIO[3:0] pins are three-stated at this time.
FIGURE 10-4:
SPI READ
SPI Read Single Register
SCK (active high)
SI
0
000
1
X
Instruction
1
Address
X
SO
d
e
c
Data
A
1
3
...
...
X
...
SPI Read Multiple Registers
00
D
7
D
6
D
5
Z
Z
X
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
5
3
5
4
5
5
5
6
X
X
5
3
5
4
5
5
5
6
D
2
6
D
2
4
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SCK (active high)
SI
0
000
1
X
Instruction
1
Address
X
SO
d
e
c
A
1
3
...
X
...
00
Z
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
X
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
D
7
D
6
D
5
D
2
6
D
2
4
...
D
7
D
6
D
5
D
2
6
D
2
4
Z
X
X
...
...
D
2
5
D
2
5
D
2
5
Data 1...
Data m
Data m+1... Data n
...



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