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LAN9252/ML 数据表(PDF) 111 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 111 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 111
LAN9252
10.2.5.1
Dual I/O Read
The SPI Dual I/O Read instruction inputs the instruction code one bit per clock and the address and dummy bytes two
bits per clock and outputs the data two bits per clock. This instruction is supported in SPI bus protocol only with clock
frequencies up to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SDIOR instruction, BBh, is input into the
SIO[0] pin, followed by the two address bytes and 2 dummy bytes into the SIO[1:0] pins. The address bytes specify a
BYTE address within the device.
On the falling clock edge following the rising edge of the last dummy di-bit, the SIO[1:0] pins are driven starting with the
msbs of the LSB of the selected register. The remaining register di-bits are shifted out on subsequent falling clock edges.
The SCS# input is brought inactive to conclude the cycle. The SIO[1:0] pins are three-stated at this time.
Figure 10-9 illustrates a typical single and multiple register dual I/O read.
FIGURE 10-9:
SPI DUAL I/O READ
SPI Dual I/O Read Single Register
SCK (active high)
SIO0
1
X
Instruction
1
Address
SIO1
d
e
c
Data
A
1
3
...
...
...
SPI Dual I/O Read Multiple Registers
10
D
7
D
6
D
5
Z
Z
X
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
7
3
8
3
9
4
0
X
X
3
7
3
8
3
9
4
0
D
2
9
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SCK (active high)
SIO0 X
Instruction
SIO1
...
...
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
...
...
...
x
x
x
x
x
x
x
x
2
5
2
6
2
7
2
5
2
6
2
7
Dummy
x
2
5
2
6
2
7
2
5
2
6
2
7
D
2
5
Data 1...
Data m
Data m+1... Data n
...
D
4
D
3
D
2
D
2
4
D
2
8
D
2
6
D
2
7
X
Data
D
7
D
6
D
5
D
4
D
3
D
2
D
2
9
D
2
5
D
2
4
D
2
8
D
2
6
D
2
7
D
7
D
6
D
5
D
4
D
3
D
2
Z
X
D
2
9
D
2
5
D
2
4
D
2
8
D
2
6
D
2
7
X
Data 1...
Data m
Data m+1... Data n
x
x
x
x
x
x
x
x
1
1
10
1
1
10
1
1
10
Address
d
e
c
A
1
3
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Z
x
x
x
x
x
x
x
x
Dummy
x
x
x
x
x
x
x
Address
Dummy
Address
Dummy



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