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LAN9252/ML 数据表(PDF) 110 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 110 Page - Microchip Technology

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LAN9252
DS00001909A-page 110
 2015 Microchip Technology Inc.
10.2.5
QUAD OUTPUT READ
The SPI Quad Output Read instruction inputs the instruction code and the address and dummy bytes one bit per clock
and outputs the data four bits per clock. This instruction is supported in SPI bus protocol only with clock frequencies up
to 80 MHz. This instruction is not supported in SQI bus protocol.
The SPI slave interface is selected by first bringing SCS# active. The 8-bit SQOR instruction, 6Bh, is input into the SIO[0]
pin, followed by the two address bytes and 1 dummy byte. The address bytes specify a BYTE address within the device.
On the falling clock edge following the rising edge of the last dummy bit, the SIO[3:0] pins are driven starting with the
msn of the LSB of the selected register. The remaining register nibbles are shifted out.
The SCS# input is brought inactive to conclude the cycle. The SIO[3:0] pins are three-stated at this time.
Figure 10-8 illustrates a typical single and multiple register quad output read.
FIGURE 10-8:
SPI QUAD OUTPUT READ
SPI Quad Output Read Single Register
SCK (active high)
SIO0
01
1
1
X
Instruction
1
Address
SIO1
d
e
c
Data
A
1
3
SPI Quad Output Read Multiple Registers
10
D
5
D
4
D
1
Z
Z
X
SCK (active low)
SCS#
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
3
3
3
4
3
5
3
7
3
8
3
9
4
0
X
X
3
7
3
8
3
9
4
0
D
1
7
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SCK (active high)
SIO0 X
Instruction
Address
SIO1
d
e
c
A
1
3
...
...
Z
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
X
X
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
...
...
...
x
x
x
x
x
x
x
x
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
Dummy
x
x
x
x
x
x
x
x
Dummy
2
5
2
6
2
7
2
8
2
9
3
0
3
1
2
5
2
6
2
7
2
8
2
9
3
0
3
1
3
2
3
2
3
3
3
4
3
5
3
3
3
4
3
5
D
2
5
Data 1...
Data m
Data m+1... Data n
...
D
0
D
1
3
D
1
2
D
2
4
D
1
6
D
2
8
D
2
9
X
Data
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
Z
X
X
Data 1...
Data m
Data m+1... Data n
SIO2
Z
...
...
Data 1...
Data m
Data m+1... Data n
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
Z
X
SIO3
Z
...
...
Data 1...
Data m
Data m+1... Data n
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
D
5
D
4
D
1
D
0
D
1
3
D
1
2
D
6
D
2
D
1
4
D
7
D
3
D
1
5
D
1
7
D
2
5
D
2
4
D
1
6
D
2
8
D
2
9
D
1
8
D
2
6
D
3
0
D
1
9
D
2
7
D
3
1
SIO2
Z
D
6
D
2
D
1
4
D
1
8
D
2
6
D
3
0
SIO3
Z
D
7
D
3
D
1
5
D
1
9
D
2
7
D
3
1
Z
X
Z
X
0
01
1
1
1
10
0
Data
Data
3
6
3
6
D
9
D
8
D
2
1
D
2
0
D
1
0
D
2
2
D
1
1
D
2
3



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