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LAN9252/ML 数据表(PDF) 113 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 113 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 113
LAN9252
10.2.6
SPI WRITE COMMANDS
Multiple write commands are support by the SPI/SQI slave. The following applies to all write commands.
MULTIPLE WRITES
Multiple reads are performed by continuing the clock pulses and input data while SCS# is active. The upper two bits of
the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The internal
DWORD address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal address
may be useful for register “bit-banging” or other repeated writes.
10.2.6.1
Write
The Write instruction inputs the instruction code and address and data bytes one bit per clock. In SQI mode, the instruc-
tion code and the address and data bytes are input four bits per clock. This instruction is supported in SPI and SQI bus
protocols with clock frequencies up to 80 MHz.
The SPI/SQI slave interface is selected by first bringing SCS# active. For SPI mode, the 8-bit WRITE instruction, 02h,
is input into the SI/SIO[0] pin, followed by the two address bytes. For SQI mode, the 8-bit WRITE instruction, 02h, is
input into the SIO[3:0] pins, followed by the two address bytes. The address bytes specify a BYTE address within the
device.
The data follows the address bytes. For SPI mode, the data is input into the SI/SIO[0] pin starting with the msb of the
LSB. For SQI mode the data is input nibble wide using SIO[3:0] starting with the msn of the LSB. The remaining bits/
nibbles are shifted in on subsequent clock edges. The data write to the register occurs after the 32-bits are input. In the
event that 32-bits are not written when the SCS# is returned high, the write is considered invalid and the register is not
affected.
The SCS# input is brought inactive to conclude the cycle.
Figure 10-11 illustrates a typical single and multiple register write for SPI mode. Figure 10-12 illustrates a typical single
and multiple register write for SQI mode.
FIGURE 10-11:
SPI WRITE
SPI Write Single Register
SCK (active high)
SI
00
00
X
Instruction
1
Address
SO
d
e
c
Data
A
1
3
...
...
SPI Write Multiple Registers
00
D
7
D
6
D
5
Z
X
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
5
3
5
4
5
5
5
6
X
X
5
3
5
4
5
5
5
6
D
2
6
D
2
4
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
SCK (active high)
SI
00
00
X
Instruction
Address
SO
d
e
c
A
1
3
...
00
Z
SCK (active low)
SCS#
...
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
1
6
2
5
2
6
2
7
X
X
i
n
c
A
1
2
A
1
1
A
1
0
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
...
D
7
D
6
D
5
D
2
6
D
2
4
...
D
7
D
6
D
5
D
2
6
D
2
4
X
...
D
2
5
D
2
5
D
2
5
Data 1...
Data m
Data m+1... Data n
...
0
1
0



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