LAN9252SLASHML datasheet(14/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 14

 2015 Microchip Technology Inc.

3.2

64-TQFP-EP Pin Assignments

FIGURE 3-2:

64-TQFP-EP PIN ASSIGNMENTS (TOP VIEW)

Note:

When an “#” is used at the end of the signal name, it indicates that the signal is active low. For example,

RST# indicates that the reset signal is active low.

The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Sec-

tion 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".

Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.

(Connect exposed pad to ground with a via field)

VS S

LAN9252

64-TQFP-EP

(To p V i e w )

CS/DIGIO13/GPI13/GPO13/MII_RXD1

A1/ALELO/OE_EXT/MII_CLK25

D11/AD11/DIGIO5/GPI5/GPO5/MII_TXD0

D12/AD12/DIGIO6/GPI6/GPO6/MII_TXD1

VDDIO

D9/AD9/LATCH_IN/SCK

A2/ALEHI/DIGIO10/GPI10/GPO10/

LINKACTLED2/MII_LINKPOL

VDDCR

D10/AD10/DIGIO4/GPI4/GPO4/MII_TXEN

A3/DIGIO11/GPI11/GPO11/MII_RXDV

A4/DIGIO12/GPI12/GPO12/MII_RXD0

WR/ENB/DIGIO14/GPI14/GPO14/MII_RXD2

D0/AD0/WD_STATE/SI/SIO0

SYNC1/LATCH1

VDDIO

RD/RD_WR/DIGIO15/GPI15/GPO15/MII_RXD3

RBIAS

VDD12TX1

VDD33TXRX1

VDD33BIAS

RXPA

TXNA

TXPA

RXNA

VDD12TX2

RXPB

RXNB

TXPB

D5/AD5/OUTVALID/SCS#

D4/AD4/DIGIO3/GPI3/GPO3/MII_LINK

TXNB

VDD33TXRX2

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