LAN9252SLASHML datasheet(4/329 Pages) MICROCHIP

4 / 329 page

LAN9252

DS00001909A-page 4

 2015 Microchip Technology Inc.

1.0

PREFACE

1.1

General Terms

TABLE 1-1:

GENERAL TERMS

Term

Description

10BASE-T

10 Mbps Ethernet, IEEE 802.3 compliant

100BASE-TX

100 Mbps Fast Ethernet, IEEE802.3u compliant

ADC

Analog-to-Digital Converter

ALR

Address Logic Resolution

Auto-Negotiation

BLW

Baseline Wander

Buffer Manager - Part of the switch fabric

BPDU

Bridge Protocol Data Unit - Messages which carry the Spanning Tree Protocol informa-

tion

Byte

8 bits

CSMA/CD

Carrier Sense Multiple Access/Collision Detect

CSR

Control and Status Registers

CTR

Counter

Destination Address

DWORD

32 bits

EPC

EEPROM Controller

FCS

Frame Check Sequence - The extra checksum characters added to the end of an

Ethernet frame, used for error detection and correction.

FIFO

First In First Out buffer

FSM

Finite State Machine

GPIO

General Purpose I/O

Host

External system (Includes processor, application software, etc.)

IGMP

Internet Group Management Protocol

Inbound

Refers to data input to the device from the host

Level-Triggered Sticky Bit

This type of status bit is set whenever the condition that it represents is asserted. The

bit remains set until the condition is no longer true and the status bit is cleared by writ-

ing a zero.

lsb

Least Significant Bit

LSB

Least Significant Byte

LVDS

Low Voltage Differential Signaling

MDI

Medium Dependent Interface

MDIX

Media Independent Interface with Crossover

MII

Media Independent Interface

MIIM

Media Independent Interface Management

MIL

MAC Interface Layer

MLD

Multicast Listening Discovery

MLT-3

Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a

change in the logic level represents a code bit “1” and the logic output remaining at the

same level represents a code bit “0”.

msb

Most Significant Bit

MSB

Most Significant Byte

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