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LAN9252/ML 数据表(PDF) 11 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 11 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 11
LAN9252
3.0
PIN DESCRIPTIONS AND CONFIGURATION
3.1
64-QFN Pin Assignments
FIGURE 3-1:
64-QFN PIN ASSIGNMENTS (TOP VIEW)
Note:
When a “#” is used at the end of the signal name, it indicates that the signal is active low. For example,
RST# indicates that the reset signal is active low.
The buffer type for each signal is indicated in the “Buffer Type” column of the pin description tables in Sec-
tion 3.3, "Pin Descriptions". A description of the buffer types is provided in Section 1.2, "Buffer Types".
Note: Exposed pad (VSS) on bottom of package must be connected to ground with a via field.
(Connect exposed pad to ground with a via field)
VSS
LAN9252
64-QFN
(Top View)
5
6
7
8
9
10
11
12
44
43
42
41
40
39
38
37
FXLOSEN
REG_EN
FXSDA/FXLOSA/FXSDENA
FXSDB/FXLOSB/FXSDENB
RST#
D2/AD2/SOF/SIO2
D1/AD1/EOF/SO/SIO1
VDDIO
LINKACTLED1/TDI/CHIP_MODE1
RUNLED/E2PSIZE
EESCL/TCK
VDDCR
D6/AD6/DIGIO0/GPI0/GPO0/MII_RXCLK
D3/AD3/WD_TRIG/SIO3
EESDA/TMS
IRQ
3
4
13
14
36
35
46
45
VDDCR
VDD33
OSCVSS
OSCVDD12
TESTMODE
D8/AD8/DIGIO2/GPI2/GPO2/MII_MDIO
D7/AD7/DIGIO1/GPI1/GPO1/MII_MDC
VDDIO
1
2
OSCO
OSCI
16
15
D13/AD13/DIGIO7/GPI7/GPO7/MII_TXD2/TX_SHIFT0
D14/AD14/DIGIO8/GPI8/GPO8/MII_TXD3/TX_SHIFT1
34
33
A0/D15/AD15/DIGIO9/GPI9/GPO9/MII_RXER
SYNC0/LATCH0
48
VDDIO
47
LINKACTLED0/TDO/CHIP_MODE0



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