LAN9252SLASHML datasheet(85/329 Pages) MICROCHIP

85 / 329 page

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DS00001909A-page 85

LAN9252

9.5.3

INDEX AND CONFIGURATION REGISTER DATA ACCESS

The host data bus can be 16 or 8-bits wide. The HBI Index registers and the HBI Configuration register are 32-bits wide

and are writable as WORDs or as BYTEs, depending upon the data mode. They do not have nor do they require

WORDs or BYTEs to DWORD conversion.

9.5.3.1

Write Cycles

A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write).

On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into the Con-

figuration register or one for the Index registers.

Depending on the bus width, either a WORD or a BYTE is written. The affected WORD or BYTE is determined by the

endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower address inputs.

Individual BYTE (in 16-bit data mode) access is not supported.

WRITES FOLLOWING INITIALIZATION

Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.

WRITES DURING AND FOLLOWING POWER MANAGEMENT

During and following any power management mode other than D0, writes from the Host Bus are ignored until after a

read cycle is performed.

9.5.3.2

Read Cycles

A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address

is used directly from the Host Bus.

At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depend-

ing on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is

determined by the endianness of the register (specified in the Host Bus Interface Configuration Register) and the lower

host address inputs.

9.5.4

INTERNAL REGISTER DATA ACCESS

The host data bus can be 16 or 8-bits wide while all internal registers are 32 bits wide. The Host Bus Interface performs

the conversion from WORDs or BYTEs to DWORD, while in 8 or 16-bit data mode. Two or four accesses within the

same DWORD are required in order to perform a write or read.

Each Data register, along with the FIFO direct address access, has a separate WORD or BYTE to DWORD conversion.

Accesses may be mixed among these (and the HBI Index and Configuration registers) without concern of data corrup-

tion.

9.5.4.1

Write Cycles

A write cycle occurs when CS and WR are active (or when ENB is active with RD_WR indicating write). The host

address from the Host Bus selects the contents of one of the Index registers. The result of this operation is captured on

the leading edge of the write cycle.

The host address inputs from the Host Bus are also captured on the leading edge of the write cycle. These are used to

increment the appropriate write BYTE / WORD counter (for 8 or 16-bit data mode described below) as well as to select

the correct DWORD assembly register.

On the trailing edge of the write cycle (either WR or CS or ENB going inactive), the host data is captured into one of the

Data registers. Depending on the bus width, either a WORD or a BYTE is captured. For 8 or 16-bit data modes, this

functions as the DWORD assembly with the affected WORD or BYTE determined by the lower host address inputs.

BYTE swapping is also done at this point based on the endianness of the register (specified in the Host Bus Interface

Configuration Register).

WRITES FOLLOWING INITIALIZATION

Following device initialization, writes from the Host Bus are ignored until after a read cycle is performed.

Note:

There are separate write BYTE / WORD counters and DWORD assembly registers for each of the three

Data Registers as well as for FIFO access.

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