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LAN9252/ML 数据表(PDF) 93 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 93 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 93
LAN9252
9.5.6.3
Internal Register Data Access
The figures in this section detail typical internal register data read and write cycles in indexed address mode for 16 and
8-bit modes. This includes an index register write followed by either a data read or write.
16-BIT READ
One of the Index Registers is set as described above. The address is then set to access the lower WORD of the corre-
sponding Data Register. Read data is driven on D[15:0] during RD active. The cycle repeats for the upper WORD of the
Data Register.
Note:
The upper WORD of Index Registers is reserved and don’t care. Therefore reads and writes to those
BYTEs are not useful.
FIGURE 9-28:
INDEXED ADDRESSING INDEX REGISTER ACCESS - 8-BIT WRITE/READ
FIGURE 9-29:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 16-BIT READ
CS
RD
WR
INDEX,2'b00
D[15:8]
A[4:0]
INDEX,2'b01
Index 7:0
D[7:0]
Index 15:8
INDEX,2'b00
INDEX,2'b01
INDEX,2'b10
INDEX,2'b11
8'hXX
8'hXX
Hi-Z
Index 7:0
Index 15:8
8'hXX
8'hXX
INDEX,2'b10
INDEX,2'b11
CS
RD
WR
INDEX,1'b0
Index 15:8
D[15:8]
A[4:1]
INDEX,1'b1
8'hXX
Index 7:0
D[7:0]
8'hXX
DATA,1'b0
Data 15:8
Data 7:0
DATA,1'b1
Data 31:24
Data 23:16



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