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LAN9252/ML 数据表(PDF) 95 Page - Microchip Technology

部件名 LAN9252/ML
功能描述  2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs
PDF  329 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

LAN9252/ML 数据表(HTML) 95 Page - Microchip Technology

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 2015 Microchip Technology Inc.
DS00001909A-page 95
LAN9252
8-BIT READ
One of the Index Registers is set as described above. The address is then set to access the lower BYTE of the corre-
sponding Data Register. Read data is driven on D[7:0] during RD active. D[15:8] pins are not used or driven. The cycle
repeats for the remaining BYTEs of the Data Register.
8-BIT WRITE
One of the Index Registers is set as described above. The address is then set to access the corresponding Data Reg-
ister. Data on D[7:0] is written on the trailing edge of WR. D[15:8] pins are not used or driven. The cycle repeats for the
remaining BYTEs of the Data Register.
FIGURE 9-32:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READ
FIGURE 9-33:
INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT WRITE
CS
RD
WR
INDEX,2'b00
D[15:8]
A[4:0]
INDEX,2'b01
Index 7:0
D[7:0]
Index 15:8
DATA,2'b00
DATA,2'b01
INDEX,2'b10
INDEX,2'b11
8'hXX
8'hXX
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DATA,2'b10
DATA,2'b11
CS
RD
WR
INDEX,2'b00
D[15:8]
A[4:0]
INDEX,2'b01
Index 7:0
D[7:0]
Index 15:8
DATA,2'b00
DATA,2'b01
INDEX,2'b10
INDEX,2'b11
8'hXX
8'hXX
Hi-Z
Data 7:0
Data 15:8
Data 23:16
Data 31:24
DATA,2'b10
DATA,2'b11



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