LAN9252SLASHML datasheet(55/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 55

LAN9252

In order for an interrupt event to trigger the external IRQ interrupt pin, the desired PHY interrupt event must be enabled

in the corresponding PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x), the PHY A Interrupt Event Enable

(PHY_INT_A_EN) and/or PHY B Interrupt Event Enable (PHY_INT_B_EN) bits of the Interrupt Enable Register

(INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configura-

tion Register (IRQ_CFG).

For additional details on the Ethernet PHY interrupts, refer to Section 11.2.7, "PHY Interrupts," on page 128.

8.2.2

POWER MANAGEMENT INTERRUPTS

Multiple Power Management Event interrupt sources are provided by the device. The top-level Power Management

Interrupt Event (PME_INT) bit of the Interrupt Status Register (INT_STS) provides indication that a Power Management

interrupt event occurred in the Power Management Control Register (PMT_CTRL).

The Power Management Control Register (PMT_CTRL) provides enabling/disabling and status of all Power Manage-

ment conditions. These include energy-detect on the PHYs and Wake-On-LAN (Perfect DA, Broadcast, Wake-up frame

or Magic Packet) detection by PHYs A&B.

In order for a Power Management interrupt event to trigger the external IRQ interrupt pin, the desired Power Manage-

ment interrupt event must be enabled in the Power Management Control Register (PMT_CTRL), the Power Manage-

ment Event Interrupt Enable (PME_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set and the IRQ

output must be enabled via the IRQ Enable (IRQ_EN) bit 8 of the Interrupt Configuration Register (IRQ_CFG).

The power management interrupts are only a portion of the power management features of the device. For additional

details on power management, refer to Section 6.3, "Power Management," on page 43.

8.2.3

GENERAL PURPOSE TIMER INTERRUPT

A GP Timer (GPT_INT) interrupt is provided in the top-level Interrupt Status Register (INT_STS) and Interrupt Enable

zero to FFFFh and is cleared when the GP Timer (GPT_INT) bit of the Interrupt Status Register (INT_STS) is written

with 1.

In order for a General Purpose Timer interrupt event to trigger the external IRQ interrupt pin, the GPT must be enabled

via the General Purpose Timer Enable (TIMER_EN) bit in the General Purpose Timer Configuration Register

(GPT_CFG), the GP Timer Interrupt Enable (GPT_INT_EN) bit of the Interrupt Enable Register (INT_EN) must be set

and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register

(IRQ_CFG).

For additional details on the General Purpose Timer, refer to Section 15.1, "General Purpose Timer," on page 297.

8.2.4

ETHERCAT INTERRUPT

The top-level EtherCAT Interrupt Event (ECAT_INT) of the Interrupt Status Register (INT_STS) provides indication that

an EtherCAT interrupt event occurred in the AL Event Request Register. The AL Event Mask Register provides

enabling/disabling of all EtherCAT interrupt conditions. The AL Event Request Register provides the status of all Ether-

CAT interrupts.

In order for an EtherCAT interrupt event to trigger the external IRQ interrupt pin, the desired EtherCAT interrupt must

be enabled in the AL Event Mask Register, the EtherCAT Interrupt Event Enable (ECAT_INT_EN) bit of the Interrupt

Enable Register (INT_EN) must be set and the IRQ output must be enabled via the IRQ Enable (IRQ_EN) bit of the

Interrupt Configuration Register (IRQ_CFG).

For additional details on the EtherCAT interrupts, refer to Section 12.0, "EtherCAT," on page 196.

8.2.5

SOFTWARE INTERRUPT

A general purpose software interrupt is provided in the top level Interrupt Status Register (INT_STS) and Interrupt

Enable Register (INT_EN). The Software Interrupt (SW_INT) bit of the Interrupt Status Register (INT_STS) is generated

when the Software Interrupt Enable (SW_INT_EN) bit of the Interrupt Enable Register (INT_EN) changes from cleared

to set (i.e. on the rising edge of the enable). This interrupt provides an easy way for software to generate an interrupt

and is designed for general software usage.

In order for a Software interrupt event to trigger the external IRQ interrupt pin, the IRQ output must be enabled via the

IRQ Enable (IRQ_EN) bit of the Interrupt Configuration Register (IRQ_CFG).

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