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LAN9252/ML 数据表(PDF) 79 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 79 Page - Microchip Technology |
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79 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 79 LAN9252 Note 1: Dual Phase Addressing Note 2: Depends on ALEHI / ALELO order. TABLE 9-1: MULTIPLEXED ADDRESSING READ CYCLE TIMING VALUES Symbol Description Min Typ max units tcsale CS Setup to ALELO, ALEHI Active Note 3, Note 2 0ns tcsrd CS Setup to RD or ENB Active 0 ns trdcs CS Hold from RD or ENB Inactive 0 ns twale ALELO, ALEHI Pulse Width 10 ns tadrs Address Setup to ALELO, ALEHI Inactive 10 ns tadrh Address Hold from ALELO, ALEHI Inactive 5 ns taleale ALELO Inactive to ALEHI Active ALEHI Inactive to ALELO Active Note 1, Note 2 0ns talerd ALELO, ALEHI Inactive to RD or ENB Active Note 2 5ns trdwrs RD_WR Setup to ENB Active Note 4 5ns trdwrh RD_WR Hold from ENB Inactive Note 4 5ns trdon RD or ENB to Data Buffer Turn On 0 ns trddv RD or ENB Active to Data Valid 30 ns trddh Data Output Hold Time from RD or ENB Inactive 0 ns trddz Data Buffer Turn Off Time from RD or ENB Inactive 9 ns tcson CS to Data Buffer Turn On 0 ns tcsdv CS Active to Data Valid 30 ns tcsdh Data Output Hold Time from CS Inactive 0 ns tcsdz Data Buffer Turn Off Time from CS Inactive 9 ns taledv ALELO, ALEHI Inactive to Data Valid Note 2 35 ns trd RD or ENB Active Time 32 ns trdcyc RD or ENB Cycle Time 45 ns trdale RD or ENB De-assertion Time before Address Phase 13 ns trdrd RD or ENB De-assertion Time before Next RD or ENB Note 5 13 ns trdwr RD De-assertion Time before Next WR Note 5, Note 6 13 ns |
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