LAN9252SLASHML datasheet(46/329 Pages) MICROCHIP

46 / 329 page

LAN9252

DS00001909A-page 46

 2015 Microchip Technology Inc.

Ensure that the device is in a state where it can safely be placed into a low power mode (all packets transmitted,

receivers disabled, packets processed / flushed, etc.)

Set the PM_SLEEP_EN bit in the Power Management Control Register (PMT_CTRL).

Upon entering any low power mode, the Device Ready (READY) bit in the Hardware Configuration Register (HW_CFG)

and the Power Management Control Register (PMT_CTRL) is forced low.

6.3.4.2

Exiting Low Power Modes

Exiting from a low power mode can be done manually or automatically.

An automatic wake-up will occur based on the events described in Section 6.3.2, "Wake-Up (PME) Notification". Auto-

matic wake-up is enabled with the Power Management Wakeup (PM_WAKE) bit in the Power Management Control

A manual wake-up is initiated by the host when:

• an HBI write (CS and WR or CS, RD_WR and ENB) is performed to the device. Although all writes are ignored

until the device has been woken and a read performed, the host should direct the write to the Byte Order Test

• an SPI/SQI cycle (SCS# low and SCK high) is performed to the device. Although all reads and writes are ignored

until the device has been woken, the host should direct the use a read of the Byte Order Test Register

(BYTE_TEST) to wake the device. Reads and writes to any other addresses should not be attempted until the

device is awake.

To determine when the host interface is functional, the Byte Order Test Register (BYTE_TEST) should be polled. Once

the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in

the Hardware Configuration Register (HW_CFG) or the Power Management Control Register (PMT_CTRL) can be

polled to determine when the device is fully awake.

For both automatic and manual wake-up, the Device Ready (READY) bit will go high once the device is returned to

power savings state D0 and the PLL has re-stabilized. The PM_MODE and PM_SLEEP_EN fields in the Power Man-

agement Control Register (PMT_CTRL) will also clear at this point.

Under normal conditions, the device will wake-up within 2 ms.

Note:

The PM_MODE field cannot be changed at the same time as the PM_SLEEP_EN bit is set and the

PM_SLEEP_EN bit cannot be set at the same time that the PM_MODE field is changed.

Note:

Upon entry into any of the power saving states the host interfaces are not functional.

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