LAN9252SLASHML datasheet(45/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 45

LAN9252

6.3.3.2

PHY Power Down

A PHY may be placed into power-down as described in Section 11.2.8, "PHY Power-Down Modes," on page 131.

6.3.3.3

LED Pins Power Down

All LED outputs may be disabled by setting the LED_DIS bit in the Power Management Control Register (PMT_CTRL)

Open-drain / open-source LEDs are un-driven. Push-pull LEDs are still driven but are set to their inactive state.

6.3.4

CHIP LEVEL POWER MANAGEMENT

The device supports power-down modes to allow applications to minimize power consumption.

Power is reduced by disabling the clocks as outlined in Table 6-2, "Power Management States". All configuration data

is saved when in any power state. Register contents are not affected unless specifically indicated in the register descrip-

tion.

There is one normal operating power state, D0, and three power saving states: D1, D2 and D3. Although appropriate

for various wake-up detection functions, the power states do not directly enable and are not enforced by these functions.

: Normal Mode - This is the normal mode of operation of this device. In this mode, all functionality is available.

This mode is entered automatically on any chip-level reset (POR, RST# pin reset, EtherCAT system reset).

: System Clocks Disabled, XTAL, PLL and network clocks enabled - In this low power mode, all clocks derived

from the PLL clock are disabled. The network clocks remain enabled if supplied by the PHYs or externally. The

crystal oscillator and the PLL remain enabled. Exit from this mode may be done manually or automatically.

This mode could be used for PHY General Power Down mode, PHY WoL mode and PHY Energy Detect Power

Down mode.

: System Clocks Disabled, PLL disable requested, XTAL enabled - In this low power mode, all clocks derived

from the PLL clock are disabled. The PLL is allowed to be disabled (and will disable if both of the PHYs are in

either Energy Detect or General Power Down). The network clocks remain enabled if supplied by the PHYs or

externally. The crystal oscillator remains enabled. Exit from this mode may be done manually or automatically.

This mode is useful for PHY Energy Detect Power Down mode and PHY WoL mode. This mode could be used

for PHY General Power Down mode.

: System Clocks Disabled, PLL disabled, XTAL disabled - In this low power mode, all clocks derived from the

PLL clock are disabled. The PLL will be disabled. External network clocks are gated off. The crystal oscillator is

disabled. Exit from this mode may be only be done manually.

This mode is useful for PHY General Power Down mode.

The Host must place the PHYs into General Power Down mode by setting the Power Down (PHY_PWR_DWN)

bit of the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) before setting this power state.

6.3.4.1

Entering Low Power Modes

To enter any of the low power modes (D1 - D3) from normal mode (D0), follow these steps:

Write the PM_MODE and PM_WAKE fields in the Power Management Control Register (PMT_CTRL) to their

desired values

Set the wake-up detection desired per Section 6.3.1, "Wake-Up Event Detection".

Set the appropriate wake-up notification per Section 6.3.2, "Wake-Up (PME) Notification".

TABLE 6-2:

POWER MANAGEMENT STATES

Clock Source

25 MHz Crystal Oscillator

OFF

PLL

ONONOFF(2)OFF

system clocks (100 MHz, 50 MHz, 25 MHz and others)

OFF

network clocks

available(1)

available(1)OFF(3)

Note

If supplied by the PHYs or externally

PLL is requested to be turned off and will disable if both of the PHYs are in either Energy Detect or General Power Down

PHY clocks are off, external clocks are gated off

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