LAN9252SLASHML datasheet(28/329 Pages) MICROCHIP

28 / 329 page

LAN9252

DS00001909A-page 28

 2015 Microchip Technology Inc.

Note 11:

Refer to Section 4.0, "Power Connections," on page 29, the device reference schematic, and the device

LANCheck schematic checklist for additional connection information.

TABLE 3-14:

JTAG PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

JTAG Test

Mux Select

TMS

VIS

JTAG test mode select

JTAG Test

Clock

TCK

VIS

JTAG test clock

JTAG Test

Data Input

TDI

VIS

JTAG data input

JTAG Test

Data Output

TDO

VO12

JTAG data output

TABLE 3-15:

CORE AND I/O POWER PIN DESCRIPTIONS

Num

Pins

Name

Symbol

Buffer

Type

Description

Regulator

+3.3 V Power

Supply

VDD33

+3.3 V power supply for internal regulators. See

Note 11.

Note:

+3.3 V must be supplied to this pin even

if the internal regulators are disabled.

+1.8 V to +3.3 V

Variable I/O

Power

VDDIO

+1.8 V to +3.3 V variable I/O power. See Note 11.

+1.2 V Digital

Core Power

Supply

VDDCR

Supplied by the on-chip regulator unless configured

for regulator off mode via REG_EN.

1 µF and 470 pF decoupling capacitors in parallel to

ground should be used on pin 6. See Note 11.

pad

Ground

VSS

Common ground. This exposed pad must be con-

nected to the ground plane with a via array.

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