LAN9252SLASHML datasheet(49/329 Pages) MICROCHIP

部件名	LAN9252/ML

功能描述	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

Scroll/Zoom	100%

制造商	MICROCHIP [Microchip Technology]

网页	http://www.microchip.com

标志

49 / 329 page

 2015 Microchip Technology Inc.

DS00001909A-page 49

LAN9252

RESERVED

3:1

RESERVED

Device Ready (READY)

When set, this bit indicates that the device is ready to be accessed. Upon

power-up, RST# reset, return from power savings states, EtherCAT chip level

or module level reset, or digital reset, the host processor may interrogate this

field as an indication that the device has stabilized and is fully active.

This rising edge of this bit will assert the Device Ready (READY) bit in

INT_STS and can cause an interrupt if enabled.

Note:

With the exception of the HW_CFG, PMT_CTRL, BYTE_TEST, and

RESET_CTL registers, read access to any internal resources is

forbidden while the READY bit is cleared. Writes to any address

are invalid until this bit is set.

Note:

This bit is identical to bit 27 of the Hardware Configuration Register

(HW_CFG).

Bits

Description

Type

Default

LAN9252/ML 数据表(PDF) 49 Page - Microchip Technology