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LAN9252/ML 数据表(PDF) 61 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 61 Page - Microchip Technology |
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61 / 329 page ![]() 2015 Microchip Technology Inc. DS00001909A-page 61 LAN9252 8.3.3 INTERRUPT ENABLE REGISTER (INT_EN) This register contains the interrupt enables for the IRQ output pin. Writing 1 to any of the bits enables the corresponding interrupt as a source for IRQ. Bits in the Interrupt Status Register (INT_STS) register will still reflect the status of the interrupt source regardless of whether the source is enabled as an interrupt in this register (with the exception of Soft- ware Interrupt Enable (SW_INT_EN). For descriptions of each interrupt, refer to the Interrupt Status Register (INT_STS) bits, which mimic the layout of this register. Offset: 05Ch Size: 32 bits Bits Description Type Default 31 Software Interrupt Enable (SW_INT_EN) R/W 0b 30 Device Ready Enable (READY_EN) R/W 0b 29 RESERVED RO - 28 RESERVED RO - 27 PHY B Interrupt Event Enable (PHY_INT_B_EN) R/W 0b 26 PHY A Interrupt Event Enable (PHY_INT_A_EN) R/W 0b 25:23 RESERVED RO - 22 RESERVED RO - 21:20 RESERVED RO - 19 GP Timer Interrupt Enable (GPT_INT_EN) R/W 0b 18 RESERVED RO - 17 Power Management Event Interrupt Enable (PME_INT_EN) R/W 0b 16:13 RESERVED RO - 12 RESERVED RO - 11:3 RESERVED RO - 2:1 RESERVED RO - 0 EtherCAT Interrupt Event Enable (ECAT_INT_EN) R/W 0b |
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