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LAN9252/ML 数据表(PDF) 29 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 29 Page - Microchip Technology |
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29 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 29 LAN9252 4.0 POWER CONNECTIONS Figure 4-1 and Figure 4-2 illustrate the device power connections for regulator enabled and disabled cases, respec- tively. Refer to the device reference schematic and the device LANCheck schematic checklist for additional information. Section 4.1 provides additional information on the devices internal voltage regulators. FIGURE 4-1: POWER CONNECTIONS - REGULATORS ENABLED +1.8 V to +3.3 V VDDCR Core Logic & PHY digital VDD12TX2 Ethernet PHY 1 Analog 1.0 µF 0.1 ESR VDD33BIAS VDD33TXRX1 VSS VDDCR Ethernet PHY 2 Analog VDD12TX1 VDD33TXRX2 Ethernet Master Bias IO Pads To PHY1 Magnetics To PHY2 Magnetics Note: Bypass and bulk caps as needed for PCB VDDIO VDD33 +3.3 V +3.3 V 470 pF Crystal Oscillator VSS PLL (exposed pad) (or separate 2.5V) (or separate 2.5V) VDDIO VDDIO VDDIO VDDIO VDDCR OSCVDD12 OSCVSS +3.3 V (IN) +1.2 V (OUT) Internal 1.2 V Core Regulator enable +3.3 V (IN) +1.2 V (OUT) Internal 1.2 V Oscillator Regulator VSS enable REG_EN (Pin 6) |
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