LAN9252SLASHML datasheet(96/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 96

 2015 Microchip Technology Inc.

8-BIT READS AND WRITES TO CONSTANT INTERNAL ADDRESS

One of the Index Registers is set as described above. A mix of reads and writes on D[7:0] follows, with each read or

write consisting of an access to all four BYTES of the corresponding Data Register.

9.5.6.4

RD_WR / ENB Control Mode Examples

The figures in this section detail read and write operations utilizing the alternative RD_WR and ENB signaling. The HBI

read/write mode is selectable via the HBI Read/Write Mode bit of the PDI Configuration Register (HBI Modes).

FIGURE 9-34:

INDEXED ADDRESSING INTERNAL REGISTER DATA ACCESS - 8-BIT READS/

WRITES CONSTANT ADDRESS

Note:

The examples in this section detail 16-bit mode with access to an Index Register. However, the RD_WR

and ENB signaling can be used identically for all other accesses including FIFO Direct Select Access.

The examples in this section show the ENB signal active-high and the RD_WR signal low for read and high

for write. The polarities of the RD_WR and ENB signals are selectable via the HBI Read, Read/Write Polar-

ity and HBI Write, Enable Polarity bits of the PDI Configuration Register (HBI Modes).

INDEX,2'b00

Index 15:8

D[15:8]

A[4:0]

INDEX,2'b01

Index 7:0

D[7:0]

DATA,2'b00

Data 7:0

DATA,2'b01

Data 15:8

DATA,2'b10

Data 23:16

DATA,2'b00

Data 7:0

DATA,2'b01

Data 15:8

DATA,2'b10

Data 23:16

Hi-Z

8'hXX

INDEX,2'b10

8'hXX

INDEX,2'b11

DATA,2'b10

Data 23:16

DATA,2'b11

Data 31:24

D[15:8]

A[4:0]

D[7:0]

DATA,2'b10

Data 23:16

DATA,2'b11

Data 31:24

DATA,2'b00

Data 7:0

DATA,2'b01

Data 15:8

DATA,2'b10

Data 23:16

DATA,2'b10

Data 23:16

DATA,2'b11

Data 31:24

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