LAN9252SLASHML datasheet(86/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 86

 2015 Microchip Technology Inc.

WRITES DURING AND FOLLOWING POWER MANAGEMENT

During and following any power management mode other than D0, writes from the Host Bus are ignored until after a

read cycle is performed.

8 AND 16-BIT ACCESS

While in 8 or 16-bit data mode, the host is required to perform two or four, 16 or 8-bit writes to complete a single DWORD

transfer. No ordering requirements exist. The host can access either the low or high WORD or BYTE first, as long as

the other write(s) is(are) performed to the remaining WORD or BYTEs.

A write BYTE / WORD counter keeps track of the number of writes. Each Data Register has its own BYTE / WORD

counter. At the trailing edge of the write cycle, the appropriate counter (based on the captured host address from above)

is incremented. Once all writes occur, a 32-bit write is performed to the internal register selected by the captured address

from above. The data that is written is selected from one of the three DWORD assembly registers based on the captured

host address from above.

All of the write BYTE / WORD counters are reset if the power management mode is set to anything other than D0.

9.5.4.2

Read Cycles

A read cycle occurs when CS and RD are active (or when ENB is active with RD_WR indicating read). The host address

from the Host Bus selects the contents of one of the Index registers. The result of this operation is used to select the

internal register to be read and also is captured on the leading edge of the read cycle.

The host address inputs from the Host Bus are also captured on the leading edge of the read cycle. These are used to

increment the appropriate read BYTE / WORD counter (for 8 or 16-bit data mode described below).

At the beginning of the read cycle, the appropriate register is selected and its data is driven onto the data pins. Depend-

ing on the bus width, either a WORD or a BYTE is read. For 8 or 16-bit data modes, the returned BYTE or WORD is

determined by the endianness of the Data register (specified in the Host Bus Interface Configuration Register) and the

lower host address inputs.

POLLING FOR INITIALIZATION COMPLETE

Before device initialization, the HBI will not return valid data. To determine when the HBI is functional, first the Host Bus

Interface Index Register 0 should be polled, then the Byte Order Test Register (BYTE_TEST) should be polled. Once

the correct pattern is read, the interface can be considered functional. At this point, the Device Ready (READY) bit in

the Hardware Configuration Register (HW_CFG) can be polled to determine when the device is fully configured.

READS DURING AND FOLLOWING POWER MANAGEMENT

During any power management mode other than D0, reads from the Host Bus are ignored. If the power management

mode changes back to D0 during an active read cycle, the tail end of the read cycle is ignored. Internal registers are not

affected and the state of the HBI does not change.

Note:

Writing the same WORD or BYTEs into the same DWORD may cause undefined or undesirable operation.

The HBI hardware does not protect against this operation.

Accessing the same internal register using two Index / Data register pairs may cause undefined or unde-

sirable operation. The HBI hardware does not protect against this operation.

Mixing reads and writes into the same Data register may cause undefined or undesirable operation. The

HBI hardware does not protect against this operation.

Note:

There are separate read BYTE / WORD counters for each of the three Data Registers as well as for FIFO

access.

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