LAN9252SLASHML datasheet(35/329 Pages) MICROCHIP

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DS00001909A-page 35

LAN9252

5.2

Special Restrictions on Back-to-Back Cycles

5.2.1

BACK-TO-BACK WRITE-READ CYCLES

It is important to note that there are specific restrictions on the timing of back-to-back host write-read operations. These

restrictions concern reading registers after any write cycle that may affect the register. In all cases there is a delay

between writing to a register and the new value becoming available to be read. In other cases, there is a delay between

writing to a register and the subsequent side effect on other registers.

In order to prevent the host from reading stale data after a write operation, minimum wait periods have been established.

These periods are specified in Table 5-2. The host processor is required to wait the specified period of time after writing

to the indicated register before reading the resource specified in the table. Note that the required wait period is depen-

dent upon the register being read after the write.

Performing “dummy” reads of the Byte Order Test Register (BYTE_TEST) register is a convenient way to guarantee that

the minimum write-to-read timing restriction is met. Table 5-2 shows the number of dummy reads that are required

before reading the register indicated. The number of BYTE_TEST reads in this table is based on the minimum cycle

timing of 45ns. For microprocessors with slower busses the number of reads may be reduced as long as the total time

is equal to, or greater than the time specified in the table. Note that dummy reads of the BYTE_TEST register are not

required as long as the minimum time period is met.

Note that depending on the host interface mode in use, the basic host interface cycle may naturally provide sufficient

time between writes and read. It is required of the system design and register access mechanisms to ensure the proper

timing. For example, a write and read to the same register may occur faster than a write and read to different registers.

For 8 and 16-bit write cycles, the wait time for the back-to-back write-read operation applies only to the writing of the

last BYTE or WORD of the register, which completes a single DWORD transfer.

For Indexed Address mode HBI operation, the wait time for the back-to-back write-read operation applies only to access

to the internal registers and FIFOs. It does not apply to the Host Bus Interface Index Registers or the Host Bus Interface

Configuration Register.

TABLE 5-2:

READ AFTER WRITE TIMING RULES

After Writing...

wait for this many

nanoseconds...

or Perform this many

Reads of BYTE_TEST…

(assuming Tcyc of 45ns)

before reading...

any register

the same register

or any other register affected

by the write

Interrupt Configuration Regis-

ter (IRQ_CFG)

Interrupt Configuration Regis-

ter (IRQ_CFG)

Interrupt Enable Register

(INT_EN)

Interrupt Configuration Regis-

ter (IRQ_CFG)

Interrupt Status Register

(INT_STS)

Interrupt Status Register

(INT_STS)

180

Interrupt Configuration Regis-

ter (IRQ_CFG)

170

Interrupt Status Register

(INT_STS)

Power Management Control

165

Power Management Control

170

Interrupt Configuration Regis-

ter (IRQ_CFG)

160

Interrupt Status Register

(INT_STS)

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