LAN9252SLASHML datasheet(41/329 Pages) MICROCHIP

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 2015 Microchip Technology Inc.

DS00001909A-page 41

LAN9252

Port A PHY Reset

A Port A PHY reset is performed by setting the PHY_A_RST bit of the Reset Control Register (RESET_CTL) or the Soft

Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port A PHY reset,

the PHY_A_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this

reset.

Port A PHY reset completion can be determined by polling the PHY_A_RST bit in the Reset Control Register

(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.

Under normal conditions, the PHY_A_RST and Soft Reset bit will clear approximately 102 uS after the Port A PHY reset

occurrence.

In addition to the methods above, the Port A PHY is automatically reset after returning from a PHY power-down mode.

This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to

Section 11.2.8, "PHY Power-Down Modes," on page 131 for additional information.

Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port A PHY resets.

If Port A PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 0 (2

port mode or 3 port downstream mode) or on port 2 (3 port upstream mode).

Port B PHY Reset

A Port B PHY reset is performed by setting the PHY_B_RST bit of the Reset Control Register (RESET_CTL) or the Soft

Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x). Upon completion of the Port B PHY reset,

the PHY_B_RST and Soft Reset bits are automatically cleared. No other modules of the device are affected by this

reset.

Port B PHY reset completion can be determined by polling the PHY_B_RST bit in the Reset Control Register

(RESET_CTL) or the Soft Reset bit in the PHY x Basic Control Register (PHY_BASIC_CONTROL_x) until it clears.

Under normal conditions, the PHY_B_RST and Soft Reset bit will clear approximately 102 us after the Port B PHY reset

occurrence.

In addition to the methods above, the Port B PHY is automatically reset after returning from a PHY power-down mode.

This reset differs in that the PHY power-down mode reset does not reload or reset any of the PHY registers. Refer to

Section 11.2.8, "PHY Power-Down Modes," on page 131 for additional information.

Refer to Section 11.2.10, "Resets," on page 135 for additional information on Port B PHY resets.

If Port B PHY is in 100BASE-FX mode, it is reset when the Enhanced link detection function detects errors on port 1.

EtherCAT Controller Reset

A compete device and system reset can be initiated by either the EtherCAT master or by the local host by writing the

value sequence of 0x52 (‘R’), 0x45 (‘E’) and 0x53 (‘S’) into the ESC Reset ECAT Register (for the master) or the ESC

Reset PDI Register (for the local host). This will trigger the reset described in Section 6.2.1.3, "EtherCAT System Reset".

A reset of just the EtherCAT Controller may be performed by setting the ETHERCAT_RST bit in the Reset Control Reg-

ister (RESET_CTL).

This will reset the EtherCAT Core and its registers. It will also reset the EtherCAT CSR and Process Data RAM Access

logic described in Section 12.11, on page 208 and will reset the registers described in Section 12.13, "EtherCAT CSR

and Process Data RAM Access Registers (Directly Addressable)," on page 214.

Since the EtherCAT module will reconfigure the device from the EEPROM, the Host interfaces will be disabled until reset

is complete. Completion of the reset must be determined by using the methods described in Section 9.4.2.2, on page 64

and Section 9.5.3.2, on page 85 for HBI and Section 10.2.1.1, on page 104 for SPI/SQI.

Note:

When using the Soft Reset bit to reset the Port A PHY, register bits designated as NASR are not reset.

Note:

When using the Soft Reset bit to reset the Port B PHY, register bits designated as NASR are not reset.

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