LAN9252SLASHML datasheet(54/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 54

 2015 Microchip Technology Inc.

(IRQ_CFG). A setting of all zeros disables the de-assertion timer. The de-assertion interval starts when the IRQ pin de-

asserts, regardless of the reason.

The following sections detail each category of interrupts and their related registers. Refer to the corresponding function’s

chapter for bit-level definitions of all interrupt registers.

8.2.1

ETHERNET PHY INTERRUPTS

The Ethernet PHYs each provide a set of identical interrupt sources. The top-level PHY A Interrupt Event (PHY_INT_A)

and PHY B Interrupt Event (PHY_INT_B) bits of the Interrupt Status Register (INT_STS) provide indication that a PHY

interrupt event occurred in the PHY x Interrupt Source Flags Register (PHY_INTERRUPT_SOURCE_x).

PHY interrupts are enabled/disabled via their respective PHY x Interrupt Mask Register (PHY_INTERRUPT_MASK_x).

The source of a PHY interrupt can be determined and cleared via the PHY x Interrupt Source Flags Register (PHY_IN-

TERRUPT_SOURCE_x). Unique interrupts are generated based on the following events:

• ENERGYON Activated

• Auto-Negotiation Complete

• Remote Fault Detected

• Link Down (Link Status Negated)

• Link Up (Link Status Asserted)

• Auto-Negotiation LP Acknowledge

• Parallel Detection Fault

• Auto-Negotiation Page Received

• Wake-on-LAN Event Detected

FIGURE 8-1:

FUNCTIONAL INTERRUPT HIERARCHY

INT_CFG

INT_STS

INT_EN

Top Level Interrupt Registers

(System CSRs)

PHY_INTERRUPT_SOURCE_B

PHY_INTERRUPT_MASK_B

PHY B Interrupt Registers

Bit 27 (PHY_INT_B)

of INT_STS register

PHY_INTERRUPT_SOURCE_A

PHY_INTERRUPT_MASK_A

PHY A Interrupt Registers

Bit 26 (PHY_INT_A)

of INT_STS register

PMT_CTRL

Power Management Control Register

Bit 17 (PME_INT)

of INT_STS register

ECAT_AL_EVENT_REQUEST

ECAT_AL_EVENT_MASK

EtherCAT Interrupt Registers

Bit 0 (ECAT_INT)

of INT_STS register

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