LAN9252SLASHML datasheet(106/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 106

 2015 Microchip Technology Inc.

10.2.4

SPI READ COMMANDS

Various read commands are support by the SPI/SQI slave. The following applies to all read commands.

MULTIPLE READS

Additional reads, beyond the first, are performed by continuing the clock pulses while SCS# is active. The upper two bits

of the address specify auto-incrementing (address[15:14]=01b) or auto-decrementing (address[15:14]=10b). The inter-

nal DWORD address is incremented, decremented, or maintained based on these bits. Maintaining a fixed internal

address is useful for register polling.

SPECIAL CSR HANDLING

Live Bits

Since data is read serially, the selected register’s value is saved at the beginning of each 32-bit read to prevent the host

from reading an intermediate value. The saving occurs multiple times in a multiple read sequence.

Change on Read Registers and FIFOs

Any register that is affected by a read operation (e.g. a clear on read bit or FIFO) is updated once the current data output

shift has started. In the event that 32-bits are not read when the SCS# is returned high, the register is still affected and

any prior data is lost.

Change on Read Live Register Bits

As described above, the current value from a register with live bits (as is the case of any register) is saved before the

data is shifted out. Although a H/W event that occurs following the data capture would still update the live bit(s), the live

bit(s) will be affected (cleared, etc.) once the output shift has started and the H/W event would be lost. In order to prevent

this, the individual CSRs defer the H/W event update until after the read indication.

10.2.4.1

Read

The Read instruction inputs the instruction code and address bytes one bit per clock and outputs the data one bit per

clock. This instruction is supported in SPI bus protocol only with clock frequencies up to 30 MHz. This instruction is not

supported in SQI bus protocol.

The SPI slave interface is selected by first bringing SCS# active. The 8-bit READ instruction, 03h, is input into the SI/

SIO[0] pin, followed by the two address bytes. The address bytes specify a BYTE address within the device.

On the falling clock edge following the rising edge of the last address bit, the SO/SIO[1] pin is driven starting with the

msb of the LSB of the selected register. The remaining register bits are shifted out on subsequent falling clock edges.

The SCS# input is brought inactive to conclude the cycle. The SO/SIO[1] pin is three-stated at this time.

FIGURE 10-3:

SQI MODE RESET SQI

SQI Mode Reset SQI

SCK (active high)

SIO[3:0]

SCK (active low)

SCS#

Inst

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