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LAN9252/ML 数据表(PDF) 237 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 237 Page - Microchip Technology |
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237 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 237 LAN9252 Note 6: The possibility of RX FIFO Size reduction depends on the clock source accuracy of the ESC and of every connected EtherCAT/Ethernet device (master, slave, etc.). RX FIFO Size of 111b is sufficient for 100ppm accuracy, RX FIFO Size 000b is possible with 25ppm accuracy (frame size of 1518/1522 Byte). Note 7: Loop configuration changes are delayed until the end of a currently received or transmitted frame at the port. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.18 PHYSICAL READ/WRITE OFFSET REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 1 Temporary Use of Register 0101h Settings 0: Permanent Use 1: Temporarily use for ~1 s, then revert to previous settings. R/W RO 0b 0 Forwarding Rule 0: EtherCAT frames are processed, Non-EtherCAT frames are forwarded without processing 1: EtherCAT frame are processed, Non-EtherCAT frames are destroyed. The source MAC address is changed for every frame (SOURCE_MAC[1] is set to 1 - locally administered address) regardless of the forwarding rule. R/W RO 1b Offset: 0108h-0109h Size: 16 bits Bits Description ECAT Type PDI Type Default 15:0 Physical Read/Write Offset Offset of R/W commands (FPRW, APRW) between Read address and Write address. RD_ADR - ADR and WR_ADR = ADR + R/W-offset. R/W RO 0b Bits Description ECAT Type PDI Type Default |
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