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LAN9252/ML 数据表(PDF) 243 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 243 Page - Microchip Technology |
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243 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 243 LAN9252 12.14.25 ESC CONFIGURATION REGISTER Note 11: The default value of this field can be configured via EEPROM. Refer to Section 12.8, "EEPROM Configu- rable Registers," on page 201 for additional information. Note: This register is initialized from the contents of the EEPROM. The EEPROM settings for Enhanced Link detection (bits 6,5,4,1) are only taken at the first EEPROM loading after power-on reset. Changing the EEPROM and manually reloading it will not affect the Enhanced link detection enable status, even if the EEPROM could not be read initially. Offset: 0141h Size: 8 bits Bits Description ECAT Type PDI Type Default 7 RESERVED RO RO 0b 6 Enhanced Link Port 2 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 5 Enhanced Link Port 1 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 4 Enhanced Link Port 0 0: Disabled (if bit 1 = 0) 1: Enabled RO RO 0b Note 11 3 Distributed Clocks Latch In Unit 0: Disabled (power saving) 1: Enabled Note: This bit has no affect. RO RO 0b 2 Distributed Clocks SYNC Out Unit 0: Disabled (power saving) 1: Enabled Note: This bit has no affect. RO RO 0b 1 Enhanced Link Detection All Ports 0: Disabled (if bits [7:4] = 0) 1: Enabled all ports RO RO 0b Note 11 0 Device Emulation (control of AL Status Register) 0: AL Status Register must be set by PDI 1: AL Status Register set to value written to AL Control Register Note: The value programmed should be 1 for Digital I/O mode and 0 for applications with a host controller. RO RO 0b Note 11 |
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