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LAN9252/ML 数据表(PDF) 286 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 286 Page - Microchip Technology |
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286 / 329 page  LAN9252 DS00001909A-page 286 2015 Microchip Technology Inc. 12.14.80 NEXT SYNC1 PULSE REGISTER Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.81 SYNC0 CYCLE TIME REGISTER Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.82 SYNC1 CYCLE TIME REGISTER Note: Writes to this register depend on the Sync Out Unit Control bit of the Cyclic Unit Control Register. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 0998h-099Fh Size: 64 bits Bits Description ECAT Type PDI Type Default 63:0 System time of next SYNC1 pulse in ns. RO RO 00000000h 00000000h Offset: 09A0h-09A3h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 Time between two consecutive SYNC0 pulses in ns. A value of 0 indicates Single shot mode - generate only one SYNC0 pulse. R/W R/W 00000000h Offset: 09A4h-09A7h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 Time between SYNC1 pulses and SYNC0 pulse in ns. R/W R/W 00000000h |
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