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LAN9252/ML 数据表(PDF) 291 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 291 Page - Microchip Technology |
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291 / 329 page  2015 Microchip Technology Inc. DS00001909A-page 291 LAN9252 12.14.91 ETHERCAT BUFFER CHANGE EVENT TIME REGISTER Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.92 PDI BUFFER START TIME EVENT REGISTER Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. 12.14.93 PDI BUFFER CHANGE EVENT TIME REGISTER Note: Register bits [31:8] are internally latched (ECAT/PDI independently) when bits [7:0] are read, which guaran- tees reading a consistent value. Note: For EtherCAT Core CSR registers longer than one byte, the LSB has the lowest address and the MSB the highest address. Offset: 09F0h-09F3h Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 This register captures the local time of the beginning of the frame which causes at least one SyncManager to assert an ECAT event. RO RO 00000000h Offset: 09F8h-09FBh Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 This register captures the local time when at least one SyncMan- ager asserts a PDI buffer start event. RO RO 00000000h Offset: 09FCh-09FFh Size: 32 bits Bits Description ECAT Type PDI Type Default 31:0 This register captures the local time when at least one SyncMan- ager asserts a PDI buffer change event. RO RO 00000000h |
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