LAN9252SLASHML datasheet(298/329 Pages) MICROCHIP

部件名	LAN9252/ML

功能描述	2/3-Port EtherCAT® Slave Controller with Integrated Ethernet PHYs

PDF	329 Pages

Scroll/Zoom	100%

制造商	MICROCHIP [Microchip Technology]

网页	http://www.microchip.com

标志

298 / 329 page

LAN9252

DS00001909A-page 298

 2015 Microchip Technology Inc.

15.3.1

GENERAL PURPOSE TIMER CONFIGURATION REGISTER (GPT_CFG)

This read/write register configures the device’s General Purpose Timer (GPT). The GPT can be configured to generate

host interrupts at the interval defined in this register. The current value of the GPT can be monitored via the General

Purpose Timer Count Register (GPT_CNT). Refer to Section 15.1, "General Purpose Timer," on page 297 for additional

information.

Offset:

08Ch

Size:

32 bits

Bits

Description

Type

Default

31:30

RESERVED

General Purpose Timer Enable (TIMER_EN)

This bit enables the GPT. When set, the GPT enters the run state. When

cleared, the GPT is halted. On the 1 to 0 transition of this bit, the GPT_LOAD

field of this register will be preset to FFFFh.

0: GPT Disabled

1: GPT Enabled

R/W

28:16

RESERVED

15:0

General Purpose Timer Pre-Load (GPT_LOAD)

This value is pre-loaded into the GPT. This is the starting value of the GPT.

The timer will begin decrementing from this value when enabled.

R/W

FFFFh

LAN9252/ML 数据表(PDF) 298 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 298 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载