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LAN9252/ML 数据表(PDF) 314 Page - Microchip Technology |
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LAN9252/ML 数据表(HTML) 314 Page - Microchip Technology |
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314 / 329 page ![]() LAN9252 DS00001909A-page 314 2015 Microchip Technology Inc. Note 23: This specification applies to all inputs and tri-stated bi-directional pins. Internal pull-down and pull-up resis- tors add ±50 µA per-pin (typical). Note 24: Measured at line side of transformer, line replaced by 100 Ω (+/- 1%) resistor. Note 25: Offset from 16 ns pulse width at 50% of pulse peak. Note 26: Measured differentially. TABLE 18-8: 100BASE-TX TRANSCEIVER CHARACTERISTICS Parameter Symbol Min Typ Max Units Notes Peak Differential Output Voltage High VPPH 950 - 1050 mVpk Note 24 Peak Differential Output Voltage Low VPPL -950 - -1050 mVpk Note 24 Signal Amplitude Symmetry VSS 98 - 102 % Note 24 Signal Rise and Fall Time TRF 3.0 - 5.0 ns Note 24 Rise and Fall Symmetry TRFS -- 0.5 ns Note 24 Duty Cycle Distortion DCD 35 50 65 % Note 25 Overshoot and Undershoot VOS -- 5 % Jitter - - - 1.4 ns Note 26 |
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