LAN9252SLASHML datasheet(150/329 Pages) MICROCHIP

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LAN9252

DS00001909A-page 150

 2015 Microchip Technology Inc.

11.2.16.5

PHY x Auto-Negotiation Advertisement Register (PHY_AN_ADV_x)

This read/write register contains the advertised ability of the PHY and is used in the Auto-Negotiation process with the

link partner.

Index (decimal): 4

Size:

16 bits

Bits

Description

Type

Default

0 = No next page ability

1 = Next page capable

R/W

RESERVED

Remote Fault

This bit determines if remote fault indication will be advertised to the link part-

ner.

0: Remote fault indication not advertised

1: Remote fault indication advertised

R/W

Extended Next Page

Note:

This bit should be written as 0.

R/W

Asymmetric Pause

This bit determines the advertised asymmetric pause capability.

0: No Asymmetric PAUSE toward link partner advertised

1: Asymmetric PAUSE toward link partner advertised

R/W

Symmetric Pause

This bit determines the advertised symmetric pause capability.

0: No Symmetric PAUSE toward link partner advertised

1: Symmetric PAUSE toward link partner advertised

R/W

RESERVED

100BASE-X Full Duplex

This bit determines the advertised 100BASE-X full duplex capability.

0: 100BASE-X full duplex ability not advertised

1: 100BASE-X full duplex ability advertised

R/W

100BASE-X Half Duplex

This bit determines the advertised 100BASE-X half duplex capability.

0: 100BASE-X half duplex ability not advertised

1: 100BASE-X half duplex ability advertised

R/W

10BASE-T Full Duplex

This bit determines the advertised 10BASE-T full duplex capability.

0: 10BASE-T full duplex ability not advertised

1: 10BASE-T full duplex ability advertised

R/W

LAN9252/ML 数据表(PDF) 150 Page - Microchip Technology

LAN9252/ML 数据表(HTML) 150 Page - Microchip Technology

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