CS5530 datasheet(160/241 Pages) NSC

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160

Revision 4.1

Index 84h

Second Level Power Management Status Mirror Register 1 (RO)

Reset Value = 40h

7:5

Reserved

Game Port SMI Status (Read Only): SMI was caused by R/W access to game port (I/O Port 200h and 201h)?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[0].

Game Port Read SMI generation enabling is at F0 Index 83h[4].

Game Port Write SMI generation enabling is at F0 Index 53h[3].

GPIO7 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO7 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[3].

GPIO5 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO5 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[2].

GPIO4 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO4 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[1].

GPIO3 SMI Status (Read Only): SMI was caused by transition on (properly-configured) GPIO3 pin?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported at F1BAR+Memory Offset 00h/02h[0].

SMI generation enabling is at F0 Index 97h[0].

Notes:

Properly-configured means that the GPIO pin must be enabled: as a GPIO (if multiplexed pin), as an input, and to cause

an SMI.

This register provides status on various power management SMI events to the SMI handler. It is called a Mirror register

since an identical register exists at F0 Index F4h. Reading this register does not clear the status, while reading its coun-

terpart at F0 Index F4h does clear the status.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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