CS5530 datasheet(156/241 Pages) NSC

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156

Revision 4.1

Index 5Eh-6Fh

Reserved

Index 70h-71h

General Purpose Chip Select Base Address Register (R/W)

Reset Value = 0000h

15:0

General Purpose Chip Select I/O Base Address: This 16-bit value represents the I/O base address used to enable the

assertion of the GPCS# signal.

This register, together with General Purpose Chip Select Control Register (F0 Index 72h) is used to configure the

operation of the GPCS# pin.

Index 72h

General Purpose Chip Select Control Register (R/W)

Reset Value = 00h

General Purpose Chip Select: GPCS# (pin AF26): 0 = Disable; 1 = Enable.

Writes Result in Chip Select: Writes to configured I/O address (base address configured in F0 Index 70h and range

configured in bits [4:0]) causes GPCS# signal to be asserted: 0 = Disable; 1 = Enable.

Reads Result in Chip Select: Reads from configured I/O address (base address configured in F0 Index 70h and range

configured in bits [4:0]) causes GPCS# signal to be asserted: 0 = Disable; 1 = Enable.

4:0

General Purpose Chip Select I/O Address Range: This 5-bit field selects the range of GPCS# signal:

00000 = 1byte

01111 = 16 bytes

00001 = 2 bytes

11111 = 32 bytes

00011 = 4 bytes

All other combinations are reserved.

00111 = 8 bytes

Note: This register, together with General Purpose Chip Select Base Address Register (F0 Index 70h) is used to configure the oper-

ation of the GPCS# pin.

Index 73h-7Fh

Reserved

Index 80h

Power Management Enable Register 1 (R/W)

Reset Value = 00h

7:6

Reserved: Set to 0.

Codec SDATA_IN SMI: Allow AC97 codec to generate an SMI due to codec producing a positive edge on SDATA_IN:

0 = Disable; 1 = Enable.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[2].

Video Speedup: Any video activity, as decoded from the serial connection (PSERIAL register, bit 0) from the GXLV

processor disables clock throttling (via SUSP#/SUSPA# handshake) for a configurable duration when the system is power

managed using CPU Suspend modulation. 0 = Disable; 1 = Enable.

The duration of the speedup is configured in the Video Speedup Timer Count Register (F0 Index 8Dh). Detection of an

external VGA access (3Bx, 3, 3Dx and A000h-B7FFh) on the PCI bus is also supported. This configuration is non-stan-

dard, but it does allow the power management routines to support an external VGA chip.

IRQ Speedup: Any unmasked IRQ (per I/O Port 021h/0A1h) or SMI disables clock throttling (via SUSP#/SUSPA# hand-

shake) for a configurable duration when the system is power managed using CPU Suspend modulation:

0 = Disable; 1 = Enable.

The duration of the speedup is configured in the IRQ Speedup Timer Count Register (F0 Index 8Ch).

Traps: Globally enable all power management device I/O traps: 0 = Disable; 1 = Enable.

This excludes the audio I/O traps. They are enabled at F3BAR+Memory Offset 18h.

Idle Timers: Globally enable all power management device idle timers: 0 = Disable; 1 = Enable.

Note, disable at this level does not reload the timers on the enable. The timers are disabled at their current counts.

This bit has no effect on the Suspend Modulation OFF/ON Timers (F0 Index 94h/95h).

Power Management: Global power management: 0 = Disable; 1 = Enabled.

This bit must be set (1) immediately after POST for power management resources to function.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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