CS5530 datasheet(152/241 Pages) NSC

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152

Revision 4.1

Index 43h

USB Shadow Register (R/W)

Reset Value = 03h

Reserved: Set to 0.

Enable SA20: Pin AD22 configuration: 0 = GPIO4; 1 = SA20. If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 =

SA20.

Legacy Cycles Assert HOLD_REQ#: Allow legacy cycles to cause HOLD_REQ# to be asserted:

0 = Disable; 1 = Enable.

Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set

to 0).

Read Cycles Assert HOLD_REQ#: Allow read cycles to cause HOLD_REQ# to be asserted:

0 = Disable; 1 = Enable.

Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set

to 0).

Any Cycle Asserts HOLD_REQ#: Allow any cycle to cause HOLD_REQ# to be asserted: 0 = Disable; 1 = Enable.

Note: The HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., disabled, set

to 0).

Enable SA[23:20]: Pins AF23, AE23, AC21, and AD22 configuration: 0 = GPIO[7:4]; 1 = SA[23:20].

If F0 Index 43h bit 6 or bit 2 is set to 1, then pin AD22 = SA20.

PCI Retry Cycles: When the CS5530 is a PCI target and the PCI buffer is not empty, allow PCI bus to retry cycles:

0 = Disable; 1 = Enable.

This bit works in conjunction with PCI bus delayed transactions bit. F0 Index 42h[5] must = 1 for this bit to be valid.

USB: USB core: 0 = Disable; 1 = Enable.

Index 44h

Reset Control Register (R/W)

Reset Value = xx000000b

ISA Mode: This bit is set to read back the strap value of the INTR pin (pin P26) during POR:

0 = ISA Limited; 1 = ISA Master.

This bit can be written after POR# deasserts to change the ISA mode selected. However, writing to this bit is not recom-

mended due to the actual strapping done on the board.

IDSEL Mode: This bit is set to read back the strap value of the HOLD_REQ# pin (pin H26) during POR:

0 = AD28 is IDSEL for Chipset Register Space and AD29 is IDSEL for USB Register Space;

1 = AD26 is IDSEL for Chipset Register Space and AD27 is IDSEL for USB Register Space.

This bit can be written after POR# deasserts to change the IDSEL settings. However, writing to this bit is not recom-

mended due to the actual strapping done on the board.

5:4

Clock 32K Control: Controls the source of the CLK_32K pin (AE3):

00 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is not output on pin AE3 (Default)

01 = CLK_32K is internally derived from CLK_14MHZ (pin P24) and is output on pin AE3

10 = CLK_32K is an input

11 = Invalid

IDE Controller Reset: Reset the IDE Controller: 0 = Disable; 1 = Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

IDE Reset: Reset IDE bus: 0 = Disable; 1 = Enable.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

PCI Reset: Reset PCI bus: 0 = Disable; 1 = Enable.

When set, the CS5530 PCI_RST# output signal (pin C14) is asserted and all devices on the PCI bus including PCIUSB

are reset. No other function within the CS5530 is affected by this bit.

Write 0 to clear. This bit is level-sensitive and must be cleared after the reset is enabled.

X-Bus Warm Start: Reading and writing this bit has two different meanings/functions:

Reading this bit: Has a warm start occurred since power-up? 0 = Yes; 1 = No

Writing this bit: 0 = NOP; 1 = Execute system wide reset (used only for clock configuration at power-up)

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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