CS5530 datasheet(150/241 Pages) NSC

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Revision 4.1

10:9

DEVSEL# Timing: These bits are always 01, as the CS5530 always responds to cycles for which it is an active target

with medium DEVSEL# timing: 00 = Fast; 01 = Medium; 10 = Slow; 11 = Reserved

Data Parity Detected: This bit is set when:

1) The CS5530 asserted PERR# or observed PERR# asserted.

2) The CS5530 is the master for the cycle in which a parity error occurred and the Parity Error bit is set (F0 Index 04h[6]

=1).

Write 1 to clear.

Fast Back-to-Back Capable: As a target, the CS5530 is capable of accepting fast back-to-back transactions:

0 = Disable; 1 = Enable.

This bit is always set to 1.

6:0

Reserved: Set to 0.

Index 08h

Device Revision ID Register (RO)

Reset Value = xxh

7:0

Device Revision ID (Read Only): 00h = Silicon Rev 1.2 or below; 13h = Silicon Rev 1.3.

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 060100h

Index 0Ch

PCI Cache Line Size Register (R/W)

Reset Value = 00h

7:0

PCI Cache Line Size Register: This register sets the size of the PCI cache line, in increments of four bytes. For memory

write and invalidate cycles, the PCI cache line size must be set to 16 bytes (04h), and the Memory Write and Invalidate bit

must be set (F0 Index 04h[4] = 1).

Index 0Dh

PCI Latency Timer Register (R/W)

Reset Value = 00h

7:4

Reserved: Set to 0.

3:0

PCI Latency Timer Value: The PCI Latency Timer Register prevents system lockup when a slave does not respond to a

cycle that the CS5530 masters. If the value is set to 00h (default), the timer is disabled. If the timer is written with any

other value, bits [3:0] become the four most significant bytes in a timer that counts PCI clocks for slave response. The

timer is reset on each valid data transfer. If the counter expires before the next assertion of TRDY# is received, the

CS5530 stops the transaction with a master abort and asserts SERR#, if enabled to do so (F0 Index 04h[8] = 1).

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

7:0

PCI Header Type Register (Read Only): This register defines the format of this header. This header is of type format 0.

Additionally, bit 7 defines whether this PCI device is a multifunction device (bit 7 = 1) or not (bit 7 = 0).

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

BIST Capable (Read Only): Is device capable of running a built-in self-test (BIST)? 0 = No; 1 = Yes,

Start BIST: Setting this bit to a one starts up a BIST on the device. The device resets this bit when the BIST has been

completed. (Not supported.)

5:4

Reserved (Read Only)

3:0

BIST Completion Code (Read Only): Upon completion of the BIST, the completion code is stored in these bits. A com-

pletion code of zero indicates the BIST has successfully been completed. All other values indicate some type of BIST fail-

ure.

Index 10h-3Fh

Reserved

Index 40h

PCI Function Control Register 1 (R/W)

Reset Value = 89h

PCI Interrupt Acknowledge Cycle Response: The CS5530 responds to PCI interrupt acknowledge cycles:

0 = Disable; 1 = Enable.

Single Write Mode: The CS5530 accepts only single cycle write transfers as a slave on the PCI bus and performs a tar-

get disconnect with the first data transferred: 0 = Disable (accepts burst write cycles); 1 = Enable.

Single Read Mode: The CS5530 accepts only single cycle read transfers as a slave on the PCI bus and performs a tar-

get disconnect with the first data transferred. 0 = Disable (accepts burst read cycles); 1 = Enable.

Retry PCI Cycles: Retry inbound PCI cycles if data is buffered and waiting to go outbound on PCI:

0 = No Retry; 1 = Retry.

Write Buffer: PCI slave write buffer: 0 = Disable; 1 = Enable.

2:1

Reserved: Set to 0.

BS8/16: This bit can not be written. Always = 1.

Note: Bits 6 and 5 emulate the behavior of first generation SIO devices developed for PCI. They should normally remain cleared.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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