CS5530 datasheet(153/241 Pages) NSC

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Index 45h-4Fh

Reserved

Index 50h

PIT Control/ISA CLK Divider (R/W)

Reset Value = 7Bh

PIT Software Reset: 0 = Disable; 1 = Enable.

PIT Counter 1: 0 = Forces Counter 1 output (OUT1) to zero; 1 = Allows Counter 1 output (OUT1) to pass to I/O

Port 061h[4].

PIT Counter 1 Enable: 0 = Sets GATE1 input low; 1 = Sets GATE1 input high.

PIT Counter 0: 0 = Forces Counter 0 output (OUT0) to zero; 1 = Allows Counter 0 output (OUT0) to pass to IRQ0.

PIT Counter 0 Enable: 0 = Sets GATE0 input low; 1 = Sets GATE0 input high.

2:0

ISA Clock Divisor: Determines the divisor of the PCI clock used to make the ISA clock, which is typically

programmed for approximately 8 MHz:

000 = Divide by one

100 = Divide by five

001 = Divide by two

101 = Divide by six

010 = Divide by three

110 = Divide by seven

011 = Divide by four

111 = Divide by eight

If PCI clock = 25 MHz, use setting of 010 (divide by 3). If PCI clock = 30 or 33 MHz, use a setting of 011 (divide by 4).

Index 51h

ISA I/O Recovery Control Register (R/W)

Reset Value = 40h

7:4

8-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 8-bit I/O read cycles. This

count is in addition to a preset one-clock delay built into the controller.

0000 = 1 PCI clock

0100 = 5 PCI clocks

1000 = 9 PCI clocks

1100 = 13 PCI clocks

0001 = 2 PCI clocks

0101 = 6 PCI clocks

1001 = 10 PCI clocks

1101 = 14 PCI clocks

0010 = 3 PCI clocks

0110 = 7 PCI clocks

1010 = 11 PCI clocks

1110 = 15 PCI clocks

0011 = 4 PCI clocks

0111 = 8 PCI clocks

1011 = 12 PCI clocks

1111 = 16 PCI clocks

3:0

16-Bit I/O Recovery: These bits determine the number of ISA bus clocks between back-to-back 16-bit I/O cycles. This

count is in addition to a preset one-clock delay built into the controller.

0000 = 1 PCI clock

0100 = 5 PCI clocks

1000 = 9 PCI clocks

1100 = 13 PCI clocks

0001 = 2 PCI clocks

0101 = 6 PCI clocks

1001 = 10 PCI clocks

1101 = 14 PCI clocks

0010 = 3 PCI clocks

0110 = 7 PCI clocks

1010 = 11 PCI clocks

1110 = 15 PCI clocks

0011 = 4 PCI clocks

0111 = 8 PCI clocks

1011 = 12 PCI clocks

1111 = 16 PCI clocks

Index 52h

ROM/AT Logic Control Register (R/W)

Reset Value = F8h

Snoop Fast Keyboard Gate A20 and Fast Reset: Enables the snoop logic associated with keyboard commands for

A20 Mask and Reset: 0 = Disable; 1 = Enable (snooping).

If disabled, the keyboard controller handles the commands.

Game Port GPORT_CS# on Writes: Allow GPORT_CS# to be asserted for writes to the game port (I/O Port 200h and

201h): 0 = Disable; 1 = Enable.

Game Port GPORT_CS# on Reads: Allow GPORT_CS# to be asserted for reads to the game port (I/O Port 200h and

201h): 0 = Disable; 1 = Enable.

Enable A20M# Deassertion on Warm Reset: Force A20M# high during a Warm Reset (guarantees that A20M# is deas-

serted regardless of the state of A20): 0 = Disable; 1 = Enable.

Enable I/O Port 092h Decode (Port A): I/O Port 092h decode and the logical functions: 0 = Disable; 1 = Enable.

Upper ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = FFFC0000h-FFFFFFFFh (256 KB, Default); 1 = FF000000h-FFFFFFFFh (16 MB)

Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]).

ROM Write Enable: Assert KBROMCS# during writes to configured ROM space (configured in bits 2 and 0),

allowing Flash programming: 0 = Disable; 1 = Enable.

Lower ROM Address Range: KBROMCS# is asserted for ISA memory read accesses:

0 = 000F0000h-000FFFFFh (64 KB, Default); 1 = 000E0000h-000FFFFFh (128 KB).

Note: PCI Positive decoding for the ROM space is enabled at F0 Index 5Bh[5]).

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

Description

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