CS5530 datasheet(155/241 Pages) NSC

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Index 5Bh

Decode Control Register 2 (R/W)

Reset Value = 20h

Keyboard I/O Port 062h/066h Decode: This alternate port to the keyboard controller is provided in support of the

8051SL notebook keyboard controller mailbox: 0 = Disable; 1 = Enable.

Reserved: Set to 0.

BIOS ROM Positive Decode: Selects PCI positive or subtractive decoding for accesses to the configured ROM space:

0 = Subtractive; 1 = Positive.

ROM configuration is at F0 Index 52h[2:0].

Secondary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 170h-

177h and 376h-377h (excluding writes to 377h): 0 = Subtractive; 1 = Positive.

Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA Bus.

Primary IDE Controller Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 1F0h-

1F7h and 3F6h-3F7h (excluding writes to 3F7h): 0 = Subtractive; 1 = Positive.

Note: Subtractive Decode mode disables this IDE controller entirely and routes any register references to the ISA Bus.

LPT3 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 3BCh-3BEh and 7BCh-

7BEh: 0 = Subtractive; 1 = Positive.

LPT2 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 278h-27Fh and

678h-67Ah: 0 = Subtractive; 1 = Positive.

LPT1 Positive Decode: Selects PCI positive or subtractive decoding for accesses to I/O Port 378h-37Fh and

778h-77Ah: 0 = Subtractive; 1 = Positive.

Note: Positive decoding by the CS5530 speeds up the I/O cycle time. The keyboard, LPT3, LPT2, and LPT1 I/O Ports do not exist in

the CS5530. It is assumed that if positive decode is enabled, the port exists on the ISA bus.

Index 5Ch

PCI Interrupt Steering Register 1 (R/W)

Reset Value = 00h

7:4

INTB# Target Interrupt: Selects target interrupt for INTB#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTA# Target Interrupt: Selects target interrupt for INTA#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

‘

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI

interrupt compatibility.

Index 5Dh

PCI Interrupt Steering Register 2 (R/W)

Reset Value = 00h

7:4

INTD# Target Interrupt: Selects target interrupt for INTD#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

3:0

INTC# Target Interrupt: Selects target interrupt for INTC#:

0000 = Disable

0100 = IRQ4

1000 = RSVD

1100 = IRQ12

0001 = IRQ1

0101 = IRQ5

1001 = IRQ9

1101 = RSVD

0010 = RSVD

0110 = IRQ6

1010 = IRQ10

1110 = IRQ14

0011 = IRQ3

0111 = IRQ7

1011 = IRQ11

1111 = IRQ15

Note: The target interrupt must first be configured as level sensitive via I/O Port 4D0h and 4D1h in order to maintain PCI

interrupt compatibility.

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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