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数据搜索系统，热门电子元器件搜索 |
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CS5530 数据表(PDF) 159 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 159 Page - National Semiconductor (TI) |
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159 / 241 page  Revision 4.1 159 www.national.com Register Descriptions (Continued) Index 83h Power Management Enable Register 4 (R/W) Reset Value = 00h 7 Secondary Hard Disk Idle Timer Enable: Turn on Secondary Hard Disk Idle Timer Count Register (F0 Index ACh) and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. If an access occurs in the address ranges selected in F0 Index 93h[4], the timer is reloaded with the programmed count. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[4]. 6 Secondary Hard Disk Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[4], an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 86h/F6h[5]. 5 ACPI Timer SMI: Allow SMI generation for MSB toggles on the ACPI Timer (F1BAR+Memory Offset 1Ch or I/O Port 121Ch in Silicon Revision 1.3 and above): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 87h/F7h[0]. 4 Game Port Read SMI: Allow SMI generation on reads to game port (I/O Port 200h and 201h): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 84h/8Fh[4]. For “Game Port Write SMI” see F0 Index 53h[3]. 3 VGA Timer Enable: Turn on VGA Timer and generate an SMI when the timer reaches 0: 0 = Disable; 1 = Enable If an access occurs in the programmed address range the timer is reloaded with the programmed count. VGA Timer programming is at F0 Index 8Eh and F0 Index 8Bh[6] SMI Status reporting is at F1BAR+Memory Offset 00h/02h[6] (only). 2 Video Retrace Interrupt SMI: Allow SMI generation whenever video retrace occurs: 0 = Disable; 1 = Enable. This information is decoded from the serial connection (PSERIAL register, bit 7) from the GXLV processor. This function is normally not used for power management but for softVGA routines. SMI status reporting is at F1BAR+Memory Offset 00h/02h[5] (only). 1 General Purpose Timer 2 (GP Timer 2) Enable: Turn on GP Timer 2 and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. This idle timer is reloaded from the assertion of GPIO7 (if programmed to do so). GP Timer 2 programming is at F0 Index 8Ah and 8Bh[5,3,2]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[1]. 0 General Purpose Timer 1 (GP Timer 1) Enable: Turn on GP Timer 1 and generate an SMI when the timer expires: 0 = Disable; 1 = Enable. This idle timer’s load is multi-sourced and is reloaded any time an enabled event (F0 Index 89h[6:0]) occurs. GP Timer 1 programming is at F0 Index 88h and 8Bh[4]. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[0] Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
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