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CS5530 数据表(PDF) 158 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5530
功能描述  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5530 数据表(HTML) 158 Page - National Semiconductor (TI)

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158
Revision 4.1
Register Descriptions (Continued)
Index 82h
Power Management Enable Register 3 (R/W)
Reset Value = 00h
7
Video Access Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the video address range (sets bit 0 of the GXLV processor’s PSERIAL
Register) an SMI is generated.
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[7].
6
User Defined Device 3 (UDEF3) Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF3 address
programming is at F0 Index C8h (base address register) and CEh (control register).
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].
Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[4].
5
User Defined Device 2 (UDEF2) Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF2 address
programming is at F0 Index C4h (base address register) and CDh (control register).
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].
Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[3].
4
User Defined Device 1 (UDEF1) Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the programmed address range an SMI is generated. UDEF1 address
programming is at F0 Index C0h (base address register), and CCh (control register).
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9].
Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[2].
3
Keyboard/Mouse Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.
Keyboard Controller: I/O Ports 060h/064h
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is included)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is included)
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[3].
2
Parallel/Serial Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.
LPT1: I/O Port 378h-37Fh, 778h-77Ah
LPT2: I/O Port 278h-27Fh, 678h-67Ah
COM1: I/O Port 3F8h-3FFh (if F0 Index 93h[1:0] = 10 this range is excluded)
COM2: I/O Port 2F8h-2FFh (if F0 Index 93h[1:0] = 11 this range is excluded)
COM3: I/O Port 3E8h-3EFh
COM4: I/O Port 2E8h-2EFh
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[2].
1
Floppy Disk Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges (listed below) an SMI is generated.
Primary floppy disk: I/O Port 3F2h-3F5h, 3F7h,
Secondary floppy disk: I/O Port 372h-375h, 377h
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[1].
0
Primary Hard Disk Trap: 0 = Disable; 1 = Enable.
If this bit is enabled and an access occurs in the address ranges selected in F0 Index 93h[5], an SMI is generated.
Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].
Second level SMI status is reported at F0 Index 86h/F6h[0].
Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)
Bit
Description



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