 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
CS5530 数据表(PDF) 151 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
CS5530 数据表(HTML) 151 Page - National Semiconductor (TI) |
|
|
151 / 241 page  Revision 4.1 151 www.national.com Register Descriptions (Continued) Index 41h PCI Function Control Register 2 (R/W) Reset Value = 10h 7 Burst to Beat: Bursts are converted to single beats for X-Bus to PCI bus reads: 0 = Disable; 1 = Enable. 6 IDE Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F2 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 5 PERR# Signals SERR#: Assert SERR# any time that PERR# is asserted or detected active by the CS5530 (allows PERR# assertion to be cascaded to NMI (SMI) generation in the system): 0 = Disable; 1 = Enable. 4 Write Buffer Enable: Allow 16-byte buffering for X-Bus to PCI bus writes: 0 = Disable; 1 = Enable. 3 Power Management Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F1 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 2:1 Subtractive Decode: These bits determine the point at which the CS5530 accepts cycles that are not claimed by another device. The CS5530 defaults to taking subtractive decode cycles in the default cycle clock, but can be moved up to the Slow Decode cycle point if all other PCI devices decode in the fast or medium clocks. Disabling subtractive decode must be done with care, as all ISA and ROM cycles are decoded subtractively. 00 = Default sample (4th clock from FRAME# active) 01 = Slow sample (3rd clock from FRAME# active) 1x = No subtractive decode 0 Legacy Configuration SMI: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the ISA Legacy I/O Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. Index 42h PCI Function Control Register 3 (R/W) Reset Value = 0Fh 7 USB SMI I/O Configuration: Route USB-generated SMI to SMI# pin: 0 = Disable; 1 = Enable, USB-generated SMI pulls SMI# pin active (low). 6 USB SMI Power Mgmnt Configuration: Route USB-generated SMI to Top Level SMI Status Register, F1BAR+Memory Offset 00h/02h[14]: 0 = Disable; 1 = Enable. 5 Delayed Transactions: Allow delayed transactions on the PCI bus: 0 = Disable; 1 = Enable. Also see F0 Index 43h[1]. 4 DMA Priority: Allow USB DMA to have priority over other DMA requests: 0 = Disable; 1 = Enable. 3 No X-Bus ARB, Buffer Enable: When the CS5530 is a PCI target, allow buffer PCI transactions without X-Bus arbitration: 0 = Disable; 1 = Enable. 2 HOLD_REQ# (Pin H26): HOLD_REQ# signal (pin H26): 0 = Disable; 1 = Enable. Note: Although the HOLD_REQ# signal function is no longer applicable, this bit must remain at its reset value (i.e., enabled, set to 1) for non-preemptive arbitration to operate correctly. 1 Video Configuration Trap: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F4 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. 0 Audio Configuration SMI: 0 = Disable; 1 = Enable. If this bit is enabled and an access occurs to one of the configuration registers in the F3 Register Space, an SMI is generated. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[9]. Second level SMI status is reported at F1BAR+Memory Offset 04h/06h[5]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
