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数据搜索系统，热门电子元器件搜索 |
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CS5530 数据表(PDF) 168 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 168 Page - National Semiconductor (TI) |
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168 / 241 page  www.national.com 168 Revision 4.1 Register Descriptions (Continued) Index 94h Suspend Modulation OFF Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Deasserted Count: This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin will be deasserted to the GXLV processor. This counter, together with the Suspend Modulation ON Count Register (F0 Index 95h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. Index 95h Suspend Modulation ON Count Register (R/W) Reset Value = 00h 7:0 Suspend Signal Asserted Count: This 8-bit counter represents the number of 32 µs intervals that the SUSP# pin will be asserted. This counter, together with the Suspend Modulation OFF Count Register (F0 Index 94h), perform the Suspend Modulation function for CPU power management. The ratio of the on-to-off count sets up an effective (emulated) clock frequency, allowing the power manager to reduce CPU power consumption. This counter is prematurely reset if an enabled speedup event occurs. The speedup events are IRQ speedups and video speedups. Index 96h Suspend Configuration Register (R/W) Reset Value = 00h 7:3 Reserved: Set to 0. 2 Suspend Mode Configuration: “Special 3 Volt Suspend” mode to support powering down a GXLV processor during Suspend: 0 = Disable; 1 = Enable. 1 SMI Speedup Configuration: Selects how Suspend Modulation function reacts when an SMI occurs: 0 = Use the IRQ Speedup Timer Count Register (F0 Index 8Ch) to temporarily disable Suspend Modulation when an SMI occurs. 1 = Disable Suspend Modulation when an SMI occurs until a read to the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The purpose of this bit is to disable Suspend Modulation while the CPU is in the System Management Mode so that VSA technology and Power Management operations occur at full speed. Two methods for accomplishing this are either to map the SMI into the IRQ Speedup Timer Count Register (F0 Index 8Ch), or to have the SMI disable Suspend Modulation until the SMI handler reads the SMI Speedup Disable Register (F1BAR+Memory Offset 08h). The latter is the preferred method. The IRQ speedup method is provided for software compatibility with earlier revisions of the CS5530. This bit has no effect if the Suspend Modulation feature is disabled (bit 0 = 0). 0 Suspend Modulation Feature Enable: Suspend Modulation feature: 0 = Disable; 1 = Enable. When enabled, the SUSP# pin will be asserted and deasserted for the durations programmed in the Suspend Modulation OFF/ON Count Registers (F0 Index 94h/95h). Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
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