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CS5530 数据表(PDF) 169 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 169 Page - National Semiconductor (TI) |
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169 / 241 page  Revision 4.1 169 www.national.com Register Descriptions (Continued) Index 97h GPIO Control Register 2 (R/W) Reset Value = 00h 7 GPIO7 Edge Sense for SMI: Selects which edge transition of the GPIO7 pin generates an SMI: 0 = Rising; 1 = Falling. Bit 3 must be set to enable this bit. 6 GPIO5 Edge Sense for SMI: Selects which edge transition of the GPIO5 pin generates an SMI: 0 = Rising; 1 = Falling. Bit 2 must be set to enable this bit. 5 GPIO4 Edge Sense for SMI: Selects which edge transition of the GPIO4 pin generates an SMI: 0 = Rising; 1 = Falling. Bit 1 must be set to enable this bit. 4 GPIO3 Edge Sense for SMI: Selects which edge transition of the GPIO3 pin will cause an external SMI: 0 = Rising; 1 = Falling. Bit 0 must be set to enable this bit. 3 Enable GPIO7 as an External SMI Source: Allow GPIO7 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 7): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[3]. 2 Enable GPIO5 as an External SMI Source: Allow GPIO5 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 6): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[2]. 1 Enable GPIO4 as an External SMI Source: Allow GPIO4 to be an external SMI source and to generate an SMI on either a rising- or falling-edge transition (depends upon setting of bit 5): 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[1]. 0 Enable GPIO3 as an External SMI Source: Allow GPIO3 to be an external SMI source and to generate an SMI on either a rising or falling edge transition (depends upon setting of bit 4) 0 = Disable; 1 = Enable. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status reporting is at F0 Index 84h/F4h[0]. Note: For any of the above bits to function properly, the respective GPIO pin must be configured as an input (F0 Index 90h). Index 98h-99h Primary Hard Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Primary Hard Disk Idle Timer Count: This idle timer is used to determine when the primary hard disk is not in use so that it can be powered down. The 16-bit value programmed here represents the period of primary hard disk inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured primary hard disk’s data port (configured in F0 Index 93h[5]). The counter uses a 1 second time- base. To enable this timer set F0 Index 81h[0] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[0]. Index 9Ah-9Bh Floppy Disk Idle Timer Count Register (R/W) Reset Value = 0000h 15:0 Floppy Disk Idle Timer Count: This idle timer is used to determine when the floppy disk drive is not in use so that it can be powered down. The 16-bit value programmed here represents the period of floppy disk drive inactivity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an access occurs to the configured floppy drive’s data port (I/O Port 3F5h or 375h). The counter uses a 1 second timebase. To enable this timer set F0 Index 81h[1] = 1. Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0]. Second level SMI status is reported at F0 Index 85h/F5h[1]. Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
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