CS5530 datasheet(171/241 Pages) NSC

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Index A6h-A7h

Video Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Video Idle Timer Count: This idle timer determines when the graphics subsystem has been idle as part of the

Suspend-determination algorithm. The 16-bit value programmed here represents the period of video inactivity after which

the system is alerted via an SMI. The count in this timer is automatically reset whenever an access occurs to the graphics

controller space. The counter uses a 1 second timebase.

In a GXLV processor based system the graphics controller is embedded in the CPU, so video activity is communicated to

the CS5530 via the serial connection (PSERIAL register, bit 0) from the processor. The CS5530 also detects accesses to

standard VGA space on PCI (3Bxh, 3h, 3Dxh and A000h-B7FFh) in the event an external VGA controller is being used.

To enable this timer set F0 Index 81h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 85h/F5h[7].

Index A8h-A9h

Video Overflow Count Register (R/W)

Reset Value = 0000h

15:0

Video Overflow Count: Each time the Video Speedup Counter (F0 Index 8Dh) is triggered, a 100 ms timer is started. If

the 100 ms timer expires before the Video Speedup Counter lapses, the Video Overflow Count Register increments and

the 100 ms timer re-triggers. Software clears the overflow register when new evaluations are to begin. The count con-

tained in this register may be combined with other data to determine the type of video accesses present in the system.

Index AAh-ABh

Reserved

Index ACh-ADh

Secondary Hard Disk Idle Timer Count Register (R/W)

Reset Value = 0000h

15:0

Secondary Hard Disk Idle Timer Count: This idle timer is used to determine when the secondary hard disk is not in use

so that it can be powered down. The 16-bit value programmed here represents the period of secondary hard disk inactiv-

ity after which the system is alerted via an SMI. The timer is automatically reloaded with the count value whenever an

access occurs to the configured secondary hard disk’s data port (configured in F0 Index 93h[4]). The counter uses a 1

second timebase.

To enable this timer set F0 Index 83h[7] = 1.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 86h/F6h[4].

Index AEh

CPU Suspend Command Register (WO)

Reset Value = 00h

7:0

Software CPU Suspend Command (Write Only): If bit 0 in the Clock Stop Control Register is set low (F0 Index BCh[0]

= 0), a write to this register causes a SUSP#/SUSPA# handshake with the CPU, placing the CPU in a low-power state.

The data written is irrelevant. Once in this state, any unmasked IRQ or SMI releases the CPU halt

condition.

If F0 Index BCh[0] = 1, writing to this register invokes a full system Suspend. In this case, the SUSP_3V pin is asserted

after the SUSP#/SUSPA# halt. Upon a Resume event (see Note), the PLL delay programmed in the F0 Index BCh[7:4] is

invoked, allowing the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are

the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external

SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to

wake-up the system from Suspend when the clocks are stopped. As long as the 32 KHz clock remains active,

internal SMI events are also Resume events.

Index AFh

Suspend Notebook Command Register (WO)

Reset Value = 00h

7:0

Software CPU Stop Clock Suspend (Write Only): A write to this register causes a SUSP#/SUSPA# handshake with the

CPU, placing the CPU in a low-power state. Following this handshake, the SUSP_3V pin is asserted. The SUSP_3V pin

is intended to be used to stop all system clocks.

Upon a Resume event (see note), the SUSP_3V pin is deasserted. After a slight delay, the CS5530 deasserts the SUSP#

signal. Once the clocks are stable, the processor deasserts SUSPA# and system operation resumes.

Note: If the clocks are stopped the external IRQ4 and IRQ3 pins, when enabled (F3BAR+Memory Offset 1Ah[4:3]), are

the only IRQ pins that can be used as a Resume event. If GPIO2, GPIO1, and GPIO0 are enabled as an external

SMI source (F0 Index 92h[2:0]), they too can be used as a Resume event. No other CS5530 pins can be used to

wake-up the system from Suspend when the clocks are stopped.

Index B0h-B3h

Reserved

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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