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Index BAh

PIT Shadow Register (RO)

Reset Value = xxh

7:0

PIT Shadow (Read Only): This 8-bit port sequences through the following list of shadowed Programmable Interval Timer

registers. At power on, a pointer starts at the first register in the list and consecutively reads to increment through it. A

write to this register resets the read sequence to the first register. Each shadow register in the sequence contains the last

data written to that location.

The read sequence for this register is:

1. Counter 0 LSB (least significant byte)

2. Counter 0 MSB

3. Counter 1 LSB

4. Counter 1 MSB

5. Counter 2 LSB

6. Counter 2 MSB

7. Counter 0 Command Word

8. Counter 1 Command Word

9. Counter 2 Command Word

Note: The LSB/MSB of the count is the Counter base value, not the current value.

Bits [7:6] of the command words are not used.

Index BBh

RTC Index Shadow Register (RO)

Reset Value = xxh

7:0

RTC Index Shadow (Read Only): The RTC Shadow register contains the last written value of the RTC Index

Index BCh

Clock Stop Control Register (R/W)

Reset Value = 00h

7:4

PLL Delay: The programmed value in this field sets the delay (in milliseconds) after a break event occurs before the

SUSP# pin is deasserted to the CPU. This delay is designed to allow the clock chip and CPU PLL to stabilize before start-

ing execution. This delay is only invoked if the STP_CLK bit (bit 0) was set.

The four-bit field allows values from 0 to 15 ms.

0000 = 0 ms

0100 = 4 ms

1000 = 8 ms

1100 = 12 ms

0001 = 1 ms

0101 = 5 ms

1001 = 9 ms

1101 = 13 ms

0010 = 2 ms

0110 = 6 ms

1010 = 10 ms

1110 = 14 ms

0011 = 3 ms

0111 = 7 ms

1011 = 11 ms

1111 = 15 ms

3:1

Reserved: Set to 0.

CPU Clock Stop: 0 = Normal SUSP#/ SUSPA# handshake; 1 = Full system Suspend.

Note: This register configures the CS5530 to support a 3 Volt Suspend. Setting bit 0 causes the SUSP_3V pin to assert after the

appropriate conditions, stopping the system clocks. A delay of 0 to 15 ms is programmable (bits 7:4) to allow for a delay for the

clock chip and CPU PLL to stabilize when an event Resumes the system.

A write to the CPU Suspend Command Register (F0 Index AEh) with bit 0 written as:

0 = SUSP#/SUSPA# handshake occurs. The CPU is put into a low-power state, and the system clocks are not stopped.

When a break/resume event occurs, it releases the CPU halt condition.

1 = SUSP#/SUSPA# handshake occurs and the SUSP_3V pin is asserted, thus invoking a full system Suspend (both CPU

and system clocks are stopped). When a break event occurs, the SUSP_3V pin will deassert, the PLL delay programmed in

bits [7:4] will be invoked which allows the clock chip and CPU PLL to stabilize before deasserting the SUSP# pin.

Index BDh-BFh

Reserved

Index C0h-C3h

User Defined Device 1 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 1 (UDEF1) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar-

ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CCh).

Index C4h-C7h

User Defined Device 2 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 2 (UDEF2) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar-

ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CDh).

Index C8h-CBh

User Defined Device 3 Base Address Register (R/W)

Reset Value = 00000000h

31:0

User Defined Device 3 (UDEF3) Base Address [31:0]: This 32-bit register supports power management (trap and idle

timer resources) for a PCMCIA slot or some other device in the system. The value written is used as the address compar-

ator for the device trap/timer logic. The device can be memory or I/O mapped (configured in F0 Index CEh).

Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued)

Bit

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