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数据搜索系统，热门电子元器件搜索 |
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CS5530 数据表(PDF) 174 Page - National Semiconductor (TI) |
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CS5530 数据表(HTML) 174 Page - National Semiconductor (TI) |
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174 / 241 page  www.national.com 174 Revision 4.1 Register Descriptions (Continued) Index CCh User Defined Device 1 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped: User Defined Device 1 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CDh User Defined Device 2 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped: User Defined Device 2 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CEh User Defined Device 3 Control Register (R/W) Reset Value = 00h 7 Memory or I/O Mapped: User Defined Device 3 is: 0 = I/O; 1 = Memory. 6:0 Mask: If bit 7 = 0 (I/O): Bit 6 0 = Disable write cycle tracking 1 = Enable write cycle tracking Bit 5 0 = Disable read cycle tracking 1 = Enable read cycle tracking Bits 4:0 Mask for address bits A[4:0] If bit 7 = 1 (M/IO): Bits 6:0 Mask for address memory bits A[15:9] (512 bytes min. and 64 KB max.) and A[8:0] are ignored. Note: A "1" in a mask bit means that the address bit is ignored for comparison. Index CFh Reserved Index D0h Software SMI Register (WO) Reset Value = 00h 7:0 Software SMI (Write Only): A write to this location generates an SMI. The data written is irrelevant. This register allows software entry into SMM via normal bus access instructions. Index D1h-EBh Reserved Index ECh Timer Test Register (R/W) Reset Value = 00h 7:0 Timer Test Value: The Timer Test Register is intended only for test and debug purposes. It is not intended for setting operational timebases. Index EDh-F3h Reserved Table 4-14. F0 Index xxh: PCI Header and Bridge Configuration Registers (Continued) Bit Description |
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