CS5530 datasheet(179/241 Pages) NSC

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4.3.2

SMI Status and ACPI Timer Registers - Function 1

The register space for the SMI status and ACPI Timer reg-

isters is divided into two sections. The first section is used

to configure the PCI portion of this support hardware. A

Base Address Register at F1 Index 10h (F1BAR) points to

the base address of where the second portion of the reg-

ister space is located. This second section contains the

SMI status and ACPI timer support registers.

Note:

In Silicon Revision 1.3 and above the ACPI Timer

Count Register is accessible through I/O Port

121Ch.

Table 4-15 shows the PCI header registers of F1. The

memory mapped registers accessed through F1BAR are

shown in Table 4-16.

Table 4-15. F1 Index xxh: PCI Header Registers for SMI Status and ACPI Timer

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0101h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:2

Reserved (Read Only)

Memory Space: Allow CS5530 to respond to memory cycles from the PCI bus: 0 = Disable; 1 = Enable.

This bit must be enabled to access memory offsets through F1BAR (F1 Index 10h).

Reserved (Read Only)

Index 06h-07h

PCI Status Register (RO)

Reset Value = 0280h

Index 08h

Device Revision ID Register (RO)

Reset Value = 00h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 068000h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-13h

Base Address Register — F1BAR (R/W)

Reset Value = 00000000h

This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h),

indicating a 256 byte memory address range. Refer to Table 4-16 for the SMI status and ACPI timer registers bit formats and reset val-

ues. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped.

Note: In Silicon Revision 1.3 and above the ACPI Timer Count Register is accessible through I/O Port 121Ch.

31:8

SMI Status/Power Management Base Address

7:0

Address Range (Read Only)

Index 14h-FFh

Reserved

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