CS5530 datasheet(183/241 Pages) NSC

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Offset 06h-07h

Second Level General Traps & Timers SMI Status Register (RC)

Reset Value = 0000h

15:6

Reserved (Read to Clear)

PCI Function Trap (Read to Clear): SMI was caused by a trapped configuration cycle (listed below)?

0= No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

Trapped Access to F1 Register Space; SMI generation enabling is at F0 Index 41h[3].

Trapped Access to F2 Register Space; SMI generation enabling is at F0 Index 41h[6].

Trapped Access to F3 Register Space; SMI generation enabling is at F0 Index 42h[0].

Trapped Access to F4 Register Space; SMI generation enabling is at F0 Index 42h[1].

Trapped Access to ISA Legacy I/O Register Space; SMI generation enabling is at F0 Index 41h[0].

SMI Source is Trapped Access to User Defined Device 3 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 3 (F0 Index C8h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[6].

SMI Source is Trapped Access to User Defined Device 2 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 2 (F0 Index C4h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[5].

SMI Source is Trapped Access to User Defined Device 1 (Read to Clear): SMI was caused by a trapped I/O or mem-

ory access to the User Defined Device 1 (F0 Index C0h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 82h[4].

SMI Source is Expired General Purpose Timer 2 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 2 (F0 Index 8Ah)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[1].

SMI Source is Expired General Purpose Timer 1 (Read to Clear): SMI was caused by the expiration of General

Purpose Timer 1 (F0 Index 88h)? 0 = No; 1 = Yes.

This is the second level of SMI status reporting. The top level is reported in F1BAR+Memory Offset 00h/02h[9].

SMI generation enabling is at F0 Index 83h[0].

Note: Reading this register clears all the SMI status bits.

A read-only “Mirror” version of this register exists at F1BAR+Memory Offset 04h. If the value of the register must be read with-

out clearing the SMI source (and consequently deasserting SMI), the Mirror register may be read instead.

Offset 08h-09h

SMI Speedup Disable Register (Read to Enable)

Reset Value = 0000h

15:0

SMI Speedup Disable: If bit 1 in the Suspend Configuration Register is set (F0 Index 96h[1] = 1), a read of this register

invokes the SMI handler to re-enable Suspend Modulation.

The data read from this register can be ignored. If the Suspend Modulation feature is disabled, reading this I/O location

has no effect.

Offset 0Ah-1Bh

Reserved

Offset 1Ch-1Fh (Note)

ACPI Timer Count Register (RO)

Reset Value = 00FFFFFCh

ACPI_COUNT (Read Only): This read-only register provides the ACPI counter. The counter counts at 14.31818/4 MHz (3.579545

MHz). If SMI generation is enabled via F0 Index 83h[5], an SMI is generated when the MSB toggles. The MSB toggles every 2.343

seconds.

Top level SMI status is reported at F1BAR+Memory Offset 00h/02h[0].

Second level SMI status is reported at F0 Index 87h/F7h[0].

31:24

Reserved: Always returns 0.

23:0

Counter

Note: The ACPI Timer Count Register is accessible through I/O Port 121Ch in Silicon Revision 1.3 and above.

Offset 20h-4Fh

Not Used

Offset

50h-FFh

The memory mapped registers located here (F1BAR+Memory Offset 50h-FFh) can also be accessed at F0 Index 50h-

FFh. The preferred method is to program these register through the F0 register space. Refer to Table 4-14 "F0 Index xxh:

PCI Header and Bridge Configuration Registers" on page 149 for bit information regarding these registers.

Table 4-16. F1BAR+Memory Offset xxh: SMI Status and ACPI Timer Registers (Continued)

Bit

Description

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