CS5530 datasheet(184/241 Pages) NSC

184 / 241 page

www.national.com

184

Revision 4.1

4.3.3

IDE Controller Registers - Function 2

The register space for the IDE controllers is divided into

two sections. The first section is used to configure the PCI

portion of the controller. A Base Address Register at F2

Index 20h points to the base address of where the second

portion of the register space is located. This second sec-

tion contains the registers used by the IDE controllers to

carry out operations.

Table 4-17 shows the PCI header registers of F2. The I/O

mapped registers, accessed through F2BAR are shown in

Table 4-18.

Table 4-17. F2 Index xxh: PCI Header Registers for IDE Configuration

Bit

Description

Index 00h-01h

Vendor Identification Register (RO)

Reset Value = 1078h

Index 02h-03h

Device Identification Register (RO)

Reset Value = 0102h

Index 04h-05h

PCI Command Register (R/W)

Reset Value = 0000h

15:3

Reserved (Read Only)

Enable Mastering: 0 = Disable, 1 = Enable

Reserved (Read Only)

I/O Space: Allow CS5530 to respond to I/O cycles from the PCI bus: 0 = Disable; 1 = Enable.

This bit must be enabled to access I/O offsets through F2BAR (F2 Index 20h).

Index 06h-07h

PCI Status Register (RO)

Reset Value = 0280h

Index 08h

Device Revision ID Register (RO)

Reset Value = 00h

Index 09h-0Bh

PCI Class Code Register (RO)

Reset Value = 010180h

Index 0Ch

PCI Cache Line Size Register (RO)

Reset Value = 00h

Index 0Dh

PCI Latency Timer Register (RO)

Reset Value = 00h

Index 0Eh

PCI Header Type (RO)

Reset Value = 00h

Index 0Fh

PCI BIST Register (RO)

Reset Value = 00h

Index 10h-1Fh

Reserved

Index 20h-23h

Base Address Register - F2BAR (R/W)

Reset Value = 00000001h

This register sets the base address of the I/O mapped bus mastering IDE and controller registers. Bits [6:0] are read only (0000 001),

indicating a 128 byte I/O address range. Refer to Table 4-18 for the IDE configuration registers bit formats and reset values.

31:7

Bus Mastering IDE Base Address

6:0

Address Range (Read Only)

Index 24h-FFh

Reserved

CS5530 数据表(PDF) 184 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 184 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5530 数据表(PDF) 184 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 184 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载