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CS5530 数据表(PDF) 186 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
部件名 CS5530
功能描述  Geode??CS5530 I/O Companion Multi-Function South Bridge
PDF  241 Pages
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制造商  NSC [National Semiconductor (TI)]
网页  http://www.national.com
标志 NSC - National Semiconductor (TI)

CS5530 数据表(HTML) 186 Page - National Semiconductor (TI)

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186
Revision 4.1
Register Descriptions (Continued)
Offset 0Ah
IDE Bus Master 1 Status Register — Secondary (R/W)
Reset Value = 00h
7
Simplex Mode (Read Only): Can both the primary and secondary channel operate independently? 0 = Yes;
1 = No (simplex mode)
6
Drive 1 DMA Capable: Allow Drive 1 to be capable of DMA transfers: 0 = Disable; 1 = Enable.
5
Drive 0 DMA Capable: Allow Drive 0 to be capable of DMA transfers: 0 = Disable; 1 = Enable.
4:3
Reserved: Set to 0. Must return 0 on reads.
2
Bus Master Interrupt: Has the bus master detected an interrupt? 0 = No; 1 = Yes.
Write 1 to clear.
1
Bus Master Error: Has the bus master detected an error during data transfer? 0 = No; 1 = Yes.
Write 1 to clear.
0
Bus Master Active (Read Only): Is the bus master active? 0 = No; 1 = Yes.
Offset 0Bh
Not Used
Offset 0Ch-0Fh
IDE Bus Master 1 PRD Table Address — Secondary (R/W)
Reset Value = 00000000h
31:2
Pointer to the Physical Region Descriptor Table: This register is a PRD table pointer for IDE Bus Master 1.
When written, this register points to the first entry in a PRD table. Once IDE Bus Master 1 is enabled (Command Register
bit 0 = 1], it loads the pointer and updates this register to the next PRD by adding 08h.
When read, this register points to the next PRD.
1:0
Reserved: Set to 0.
Offset 10h-1Fh
Not Used
Offset 20h-23h
Channel 0 Drive 0 PIO Register (R/W)
Reset Value = 0000E132h (Note)
If Offset 24h[31] = 0, Format 0: Selects slowest PIOMODE per channel for commands.
Format 0 settings for: PIO Mode 0 = 00009172h
PIO Mode 1 = 00012171h
PIO Mode 2 = 00020080h
PIO Mode 3 = 00032010h
PIO Mode 4 = 00040010h
31:20
Reserved: Set to 0.
19:16
PIOMODE: PIO mode
15:12
t2I: Recovery time (value + 1 cycle)
11:8
t3: IDE_IOW# data setup time (value + 1 cycle)
7:4
t2W: IDE_IOW# width minus t3 (value + 1 cycle)
3:0
t1: Address Setup Time (value + 1 cycle)
If Offset 24h[31] = 1, Format 1: Allows independent control of command and data.
Format 1 settings for: PIO Mode 0 = 9172D132h
PIO Mode 1 = 21717121h
PIO Mode 2 = 00803020h
PIO Mode 3 = 20102010h
PIO Mode 4 = 00100010h
31:28
t2IC: Command cycle recovery time (value + 1 cycle)
27:24
t3C: Command cycle IDE_IOW# data setup (value + 1 cycle)
23:20
t2WC: Command cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)
19:16
t1C: Command cycle address setup time (value + 1 cycle)
15:12
t2ID: Data cycle recovery time (value + 1 cycle)
11:8
t3D: Data cycle IDE_IOW# data setup (value + 1 cycle)
7:4
t2WD: Data cycle IDE_IOW# pulse width minus t3 (value + 1 cycle)
3:0
t1D: Data cycle address Setup Time (value + 1 cycle)
Note: The reset value of this register is not a valid PIO Mode.
Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued)
Bit
Description



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