CS5530 datasheet(187/241 Pages) NSC

187 / 241 page

Revision 4.1

187

www.national.com

Offset 24h-27h

Channel 0 Drive 0 DMA Control Register (R/W)

Reset Value = 00017771h

If bit 20 = 0, Multiword DMA

Settings for:

Multiword DMA Mode 0 = 00077771h

Multiword DMA Mode 1 = 00012121h

Multiword DMA Mode 2 = 00002020h

PIO Mode Format: 0 = Format 0; 1 = Format 1

30:21

Reserved: Set to 0.

DMA Select: DMA operation: 0 = Multiword DMA; 1 = Ultra DMA.

19:16

tKR: IDE_IOR# recovery time (4-bit) (value + 1 cycle)

15:12

tDR: IDE_IOR# pulse width (value + 1 cycle)

11:8

tKW: IDE_IOW# recovery time (4-bit) (value + 1 cycle)

7:4

tDW: IDE_IOW# pulse width (value + 1 cycle)

3:0

tM: IDE_CS0#/CS1# to IDE_IOR#/IOW# setup; IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1#

If bit 20= 1, UltraDMA

Settings for:

Ultra DMA Mode 0 = 00921250h

Ultra DMA Mode 1 = 00911140h

Ultra DMA Mode 2 = 00911030h

PIO Mode Format: 0 = Format 0; 1 = Format 1

30:21

Reserved: Set to 0.

DMA Select: DMA operation: 0 = Multiword DMA, 1 = Ultra DMA.

19:16

tCRC: CRC setup UDMA in IDE_DACK# (value + 1 cycle) (for host terminate CRC setup = tMLI + tSS)

15:12

tSS: UDMA out (value + 1 cycle)

11:8

tCYC: Data setup and cycle time UDMA out (value + 2 cycles)

7:4

tRP: Ready to pause time (value + 1 cycle). Note: tRFS + 1 tRP on next clock.

3:0

tACK: IDE_CS0#/CS1# setup to IDE_DACK0#/DACK1# (value + 1 cycle)

Offset 28h-2Bh

Channel 0 Drive 1 PIO Register (R/W)

Reset Value = 0000E132h

Channel 0 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

Offset 2Ch-2Fh

Channel 0 Drive 1 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 0 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

Offset 30h-33h

Channel 1 Drive 0 PIO Register (R/W)

Reset Value = 0000E132h

Channel 1 Drive 0 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

Offset 34h-37h

Channel 1 Drive 0 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 1 Drive 0 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

Offset 38h-3Bh

Channel 1 Drive 1 PIO Register (R/W)

Reset Value = 0000E132h

Channel 1 Drive 1 Programmed I/O Control Register: Refer to F2BAR+I/O Offset 20h for bit descriptions.

Offset 3Ch-3Fh

Channel 1 Drive 1 DMA Control Register (R/W)

Reset Value = 00017771h

Channel 1 Drive 1 MDMA/UDMA Control Register: Refer to F2BAR+I/O Offset 24h for bit descriptions.

Note: Once the PIO Mode Format is selected in F2BAR+I/O Offset 24h[31], bit 31 of this register is defined as reserved, read only.

Table 4-18. F2BAR+I/O Offset xxh: IDE Configuration Registers (Continued)

Bit

Description

CS5530 数据表(PDF) 187 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 187 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

CS5530 数据表(PDF) 187 Page - National Semiconductor (TI)

CS5530 数据表(HTML) 187 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载